Md Rezwanur Rahman

US Patent:

7437531, Oct 14, 2008

Filed:

Sep 30, 2004

Appl. No.:

10/955420

Inventors:

Michael Spica - Hillsboro OR, US
Hehching Harry Li - Portland OR, US
Md Rezwanur Rahman - Hillsboro OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/02
G11C 29/18
G01R 31/28

US Classification:

711217, 714718, 714728

Abstract:

Methods and apparatus to test memories, such as, for example, caches of processors, are disclosed. In one aspect, an apparatus may include a pseudo random address generation unit, such as, for example, including a linear feedback shift register, to generate pseudo random memory addresses, and a deterministic data generation unit, such as, for example, including a state machine, to generate deterministic data to be written to the pseudo random memory addresses. Computer systems and other electronic systems including such apparatus are also disclosed.

US Patent:

7777507, Aug 17, 2010

Filed:

Mar 26, 2007

Appl. No.:

11/691480

Inventors:

Daniel Richard Bockelman - Tigard OR, US
Yuan-Chuan Steven Chen - Portland OR, US
Christopher John Brookreson - Saint Helens OR, US
Md Asifur Rahman - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G01R 31/302
G01R 31/26

US Classification:

324752, 324765

Abstract:

A diagnostic tool for testing an integrated circuit device directs a beam of laser energy to stimulate at least a portion of the device. In one mode, electromagnetic waves from said device may be detected at the same time in response to the stimulation. A processor collects image data and determines as a function of the collected image data whether the device has a defect. Other embodiments are described and claimed.

US Patent:

20200105324, Apr 2, 2020

Filed:

Sep 27, 2018

Appl. No.:

16/143816

Inventors:

- Santa Clara CA, US
Sasikanth Manipatruni - Portland OR, US
MD Tofizur Rahman - Portland OR, US
Noriyuki Sato - Hillsboro OR, US
Christopher Wiegand - Portland OR, US
Ian Young - Portland OR, US

Assignee:

INTEL CORPORATION - Santa Clara CA

International Classification:

G11C 11/16
H01L 43/10
H01L 43/08
H01L 27/22

Abstract:

A magnetic tunnel junction (MTJ) for use in a magnetic spin orbit torque random access memory device (SOT MRAM) is described. Magnetic tunnel junctions described herein include a multi-magnet free layer over a spin orbit torque electrode. The multi-magnet free layer includes at least three sub-layers: a first magnetic sub-layer in direct contact with the SOT electrode having a first magnetic stability, a second magnetic sub-layer having a second magnetic stability greater than the first magnetic stability, and a magnetic coupling layer between the first and second sub-layers.

US Patent:

20200006637, Jan 2, 2020

Filed:

Jun 29, 2018

Appl. No.:

16/024714

Inventors:

- Santa Clara CA, US
Sasikanth MANIPATRUNI - Portland OR, US
Chia-Ching LIN - Portland OR, US
Kaan OGUZ - Beaverton OR, US
Christopher WIEGAND - Portland OR, US
Angeline SMITH - Hillsboro OR, US
Noriyuki SATO - Hillsboro OR, US
Kevin O'BRIEN - Portland OR, US
Benjamin BUFORD - Hillsboro OR, US
Ian YOUNG - Portland OR, US
MD Tofizur RAHMAN - Portland OR, US

International Classification:

H01L 43/02
H01L 27/22
H01L 43/12

Abstract:

Embodiments herein relate to a system, apparatus, and/or process for producing a spin orbit torque (SOT) electrode that includes a first layer with a first side to couple with a free layer of a magnetic tunnel junction (MTJ) and a second layer coupled with a second side of the first layer opposite the first side, where a value of an electrical resistance in the first SOT layer is lower than a value of an electrical resistance in the second SOT layer and where a current applied to the SOT electrode is to cause current to preferentially flow in the first SOT layer to cause a magnetic polarization of the free layer to change directions. During production of the SOT electrode, the second layer may act as an etch stop.

US Patent:

20190288190, Sep 19, 2019

Filed:

Jun 3, 2019

Appl. No.:

16/430201

Inventors:

- Santa Clara CA, US
Kevin P. O'Brien - Portland OR, US
Christopher J. Wiegand - Portland OR, US
MD Tofizur Rahman - Portland OR, US
Brian S. Doyle - Portland OR, US
Mark L. Doczy - Portland OR, US
Oleg Golonzka - Beaverton OR, US
Tahir Ghani - Portland OR, US
Justin S. Brockman - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 43/12
G11C 11/16
H01L 43/10
H01F 10/32
H01F 41/30
H01L 43/08

Abstract:

MTJ material stacks, pSTTM devices employing such stacks, and computing platforms employing such pSTTM devices. In some embodiments, perpendicular MTJ material stacks include a multi-layered filter stack disposed between a fixed magnetic layer and an antiferromagnetic layer or synthetic antiferromagnetic (SAF) stack. In some embodiments, non-magnetic layers of the filter stack include at least one of Ta, Mo, Nb, W, or Hf. These transition metals may be in pure form or alloyed with other constituents.

US Patent:

20190280188, Sep 12, 2019

Filed:

Dec 28, 2016

Appl. No.:

16/348364

Inventors:

- Santa Clara CA, US
Christopher WIEGAND - Portland OR, US
MD Tofizur RAHMAN - Portland OR, US
Daniel OUELETTE - Portland OR, US
Angeline SMITH - Hillsboro OR, US
Juan ALZATE VINASCO - Portland OR, US
Charles KUO - Hillsboro OR, US
Mark DOCZY - Portland OR, US
Kaan OGUZ - Beaverton OR, US
Kevin O'BRIEN - Portland OR, US
Brian DOYLE - Portland OR, US
Oleg GOLONZKA - Beaverton OR, US
Tahir GHANI - Portland OR, US

International Classification:

H01L 43/02
H01F 10/32
G11C 11/16
H01L 43/12
H01F 41/30

Abstract:

An apparatus comprises a magnetic tunnel junction (MTJ) including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier between the free and fixed layers, the tunnel barrier directly contacting a first side of the free layer, a capping layer contacting the second side of the free magnetic layer and boron absorption layer positioned a fixed distance above the capping layer.

US Patent:

20190221734, Jul 18, 2019

Filed:

Sep 30, 2016

Appl. No.:

16/327603

Inventors:

- Santa Clara CA, US
Kevin P. O'Brien - Portland OR, US
Brian S. Doyle - Portland OR, US
Mark L. Doczy - Beaverton OR, US
Charles C. Kuo - Hillsboro OR, US
Daniel G. Ouellette - Portland OR, US
Christopher J. Wiegand - Portland OR, US
MD Tofizur Rahman - Portland OR, US
Brian Maertz - Santa Barbara OR, US

Assignee:

INTEL CORPORATION - Santa Clara CA

International Classification:

H01L 43/08
H01L 43/10
H01L 43/12
H01L 27/22

Abstract:

Systems, apparatus, and methods for magnetoresitive memory are described. An apparatus for magnetoresitive memory includes a fixed layer, a free layer, and a tunneling barrier between the fixed layer and the free layer. The free layer is a new alloy consisting of a composition of Cobalt (Co), Iron (Fe), and Boron (B) intermixed with a non-magnetic metal according to a ratio. A thin insert layer of CoFeB may optionally be added between the alloy and the tunneling barrier.

US Patent:

20190049514, Feb 14, 2019

Filed:

Apr 1, 2016

Appl. No.:

16/073688

Inventors:

- Santa Clara CA, US
KAAN OGUZ - Beaverton OR, US
CHRISTOPHER J. WIEGAND - Portland OR, US
MARK L. DOCZY - Beaverton OR, US
BRIAN S. DOYLE - Portland OR, US
MD TOFIZUR RAHMAN - Portland OR, US
OLEG GOLONZKA - BEAVERTON OR, US
TAHIR GHANI - PORTLAND OR, US

Assignee:

INTEL CORPORATION - Santa Clara CA

International Classification:

G01R 31/28
G01R 31/315
H01L 21/66
G01R 33/09
H01L 43/12

Abstract:

Techniques are disclosed for carrying out ferromagnetic resonance (FMR) testing on whole wafers populated with one or more buried magnetic layers. The techniques can be used to verify or troubleshoot processes for forming the buried magnetic layers, without requiring the wafer to be broken. The techniques can also be used to distinguish one magnetic layer from others in the same stack, based on a unique frequency response of that layer. One example methodology includes moving a wafer proximate to a waveguide (within 500 microns, but without shorting), energizing a DC magnetic field near the target measurement point, applying an RF input signal through the waveguide, collecting resonance spectra of the frequency response of the waveguide, and decomposing the resonance spectra into magnetic properties of the target layer. One or both of the DC magnetic field and RF input signal can be swept to generate a robust set of resonance spectra.

Address:

7916 Ladera Verde Dr, Austin, TX 78739

VIN:

5FNRL38767B051113

Make:

HONDA

Model:

ODYSSEY

Year:

2007