Richard P Mann

US Patent:

6486522, Nov 26, 2002

Filed:

Sep 28, 1999

Appl. No.:

09/407741

Inventors:

Magued Bishay - Costa Mesa CA
Randall M. Chung - Laguna Niguel CA
James K. Dawson - Huntington Beach CA
David Escobar - San Juan Capistrano CA
Mike Fukatsu - La Mirada CA
Edward Andrew Jakl - Tustin CA
Richard Arthur Mann - Torrance CA
Sarit Neter - Irvine CA
Ian Olsen - Irvine CA
Gregory A. Urban - Las Flores CA

Assignee:

Pictos Technologies, Inc. - Newport Beach CA

International Classification:

H01L 3100

US Classification:

257444, 257431

Abstract:

The invention is an imaging device having a high fill factor. The high fill factor is achieved by constructing the light sensors in a vertical fashion in the imaging device. The control circuitry of the light sensor is then contained inside the integrated circuit chip, rather than taking up area that could otherwise be used for light collection. The majority of the area on the surface of the IC chip is made up of light sensing elements, since the control circuitry is embedded in the IC chip. The control circuitry is connected to the light sensing devices through vias in the IC chip. The control circuitry of the chip is mainly contained within the die, rather than on it.

US Patent:

6617562, Sep 9, 2003

Filed:

Oct 5, 2000

Appl. No.:

09/680037

Inventors:

Richard A. Mann - Torrance CA

Assignee:

Pictos Technologies, Inc. - Newport Beach CA

International Classification:

H01L 2700

US Classification:

2502081, 250214 R, 257290, 257291

Abstract:

An image sensor having a photo-detector and a reset contact that are electrically connected by a discharge path disposed between the reset contact and the photo-detector. The photo-detector has a depletion region for receiving and collecting radiation charges that are discharged through the discharge path to the reset contact. In one implementation, the reset of the photo-detector to a known potential is achieved by applying a high reset voltage to the reset contact that causes a reset depletion region to form beneath the reset contact. The outer perimeter of the reset depletion region defines a reset junction. The reset junction and the photo-detector junction are of the same polarity. As the high reset voltage is increased at the reset junction, the reset depletion region merges via punch through with the photo-detectors depletion region to create the discharge path. The voltage on the reset contact is increased beyond the expected potential of the photo-detector so that a potential difference is established across the discharge path and charges are swept away from the photo-detector via the discharge path. At the end of the reset, the potential on the reset junction is reduced and the depletion regions separate and the photo detector is left with a fixed potential.

US Patent:

6639204, Oct 28, 2003

Filed:

Jul 6, 2001

Appl. No.:

09/900732

Inventors:

Richard A. Mann - Torrance CA

Assignee:

Pictos Technologies, Inc. - Newport Beach CA

International Classification:

G01J 350

US Classification:

250226, 257440

Abstract:

A solid state color imager with preferential response to two or more colors of light includes a first color-selective photoreceptor built in part from a first color-selective semiconductor region limited in depth according to a first color fractional absorption ratio for a first color of light, as well as a second color-selective photoreceptor built in part from a second color-selective semiconductor region limited in depth according to a second color fractional absorption ratio for a second color of light. The imager may provide a light shield above the second color-selective semiconductor region and position the second color-selective photoreceptor in proximity to the first color-selective photoreceptor. The second color-selective photoreceptor may then collect electrons diffusing from the first color-selective photoreceptor and generated by the second color of light. The imager need not include conventional color filters and thus provides a more cost effective color imager for human color vision applications (e. g.

US Patent:

6768149, Jul 27, 2004

Filed:

Oct 5, 2000

Appl. No.:

09/680036

Inventors:

Richard A. Mann - Torrance CA
Lester J. Kozlowski - Simi Valley CA

Assignee:

ESS Technology, Inc. - Fremont CA

International Classification:

H01L 31062

US Classification:

257292, 257291, 257293, 257294, 438 48, 438 60, 438 69, 2502081, 2502141

Abstract:

A sensor may be formed with a transistor comprising a gate that has both n-type and p-type regions to increase the gate work function. In combination with moving the p-type well such that the p-type well only partially dopes the channel of the transistor, the increased gate work function further increases the reset voltage level required to create the reset channel without having to use high doping levels in the critical regions of the sensor structure including the photo-detector and the reset transistor. The source of the reset transistor is partially beneath the n-type region of gate, while the transistors drain is partially beneath the p-type region of the gate. The channel has a p-type well portion and a substrate portion. This construction of the sensor may eliminate the reset noise associated with the uncertainty of whether the charge left in the transistors channel will flow back towards the photo-detector after the transistor has been turned off.

US Patent:

6816196, Nov 9, 2004

Filed:

Jun 18, 2001

Appl. No.:

09/885433

Inventors:

Richard A. Mann - Torrance CA

Assignee:

ESS Technology, Inc. - Fremont CA

International Classification:

H04N 5217

US Classification:

348243, 348241

Abstract:

A CMOS imager includes a CMOS image sensor comprising an array of photoreceptors, a memory storing a reference operating level for the array, and readout circuitry for obtaining, at n-bit resolution, a photoreceptor reset value from the photoreceptors in the array. In addition, the CMOS imager includes comparison circuitry that determines a difference between the reference operating level and the photoreceptor reset value as well as matching circuitry that matches the difference against bins in a bin allocation. In particular, the bin allocation spans a photoreceptor noise range with the bins forming a quantization of the noise range into correction levels. Each of the correction levels may be associated with an m-bit correction code, where m is typically much less than n. As a result, the amount of memory necessary to store the correction codes is far less than that required to store full resolution (i. e. , n-bit) values.

US Patent:

6838651, Jan 4, 2005

Filed:

Mar 28, 2002

Appl. No.:

10/113545

Inventors:

Richard A. Mann - Torrance CA, US

Assignee:

ESS Technology, Inc. - Fremont CA

International Classification:

H01L 2700

US Classification:

2502081, 250214 DC, 250226

Abstract:

The present invention is directed to a solid state imaging device comprising a red pixel, a blue pixel, a first green pixel, a second green pixel, two analog-to-digital converters and a color interpolation circuit. The first analog-to-digital converter converts the output of the red pixel and output of the blue pixel into digital signals. The second analog-to-digital converter converts the output of the first green pixel and output of the second green pixel into digital signals. The color interpolation circuit combines the digital signals to determine the color of the pixel. The solid state imaging device may further comprise a third analog-to-digital converter, a fourth analog-to-digital converter, a programmable clock generator and a control. The third analog-to-digital converter converts the output of the blue pixel into a digital signal and the fourth analog-to-digital converter converts the output of the second green pixel into a digital signal. The programmable clock generator has a first clock frequency and a second clock frequency, where the first clock frequency is slower than the second clock frequency.

US Patent:

6838715, Jan 4, 2005

Filed:

Apr 29, 2003

Appl. No.:

10/425488

Inventors:

Selim Bencuya - Irvine CA, US
Richard Mann - Torrance CA, US
Erik Stauber - San Diego CA, US

Assignee:

ESS Technology, Inc. - Fremont CA

International Classification:

H01L 31062

US Classification:

257291, 257184, 257187, 257203, 257292, 257293, 257433, 257461, 257462, 257929

Abstract:

An exemplary CMOS image sensor comprises a plurality of pixels arranged in an array. The plurality of pixels includes a first pixel proximate an optical center of the array, and a second pixel proximate a peripheral edge of the array. The CMOS image sensor further comprises a first metal interconnect segment associated with the first pixel situated in a first metal layer, and a second metal interconnect segment associated with the second pixel situated in the first metal layer. The second metal interconnect segment is shifted closer to the optical center of the array than the first metal interconnect segment so that the second metal interconnect segment approximately aligns with a principle ray angle incident the second pixel, thereby reducing pixel light shadowing.

US Patent:

6902945, Jun 7, 2005

Filed:

Apr 10, 2002

Appl. No.:

10/119982

Inventors:

Richard A. Mann - Torrance CA, US
Lester J. Kozlowski - Simi Valley CA, US

Assignee:

ESS Technology, Inc. - Fremont CA

International Classification:

H01L021/00
H01L031/062

US Classification:

438 48, 438 57, 438 76, 438 77, 438 78, 257291, 257292, 257293, 257294, 2502141, 2502081, 2502082

Abstract:

A sensor may be formed with a transistor comprising a gate that has both n-type and p-type regions to increase the gate work function. In combination with moving the p-type well such that the p-type well only partially dopes the channel of the transistor, the increased gate work function further increases the reset voltage level required to create the reset channel without having to use high doping levels in the critical regions of the sensor structure including the photo-detector and the reset transistor. The source of the reset transistor is partially beneath the n-type region of gate, while the transistor's drain is partially beneath the p-type region of the gate. The channel has a p-type well portion and a substrate portion. This construction of the sensor may eliminate the reset noise associated with the uncertainty of whether the charge left in the transistor's channel will flow back towards the photo-detector after the transistor has been turned off.