Robert C Kim

US Patent:

6976423, Dec 20, 2005

Filed:

May 12, 2004

Appl. No.:

10/843710

Inventors:

Robert H. Kim - Gardena CA, US
Kwan B. Lee - Gardena CA, US

International Classification:

B41D007/00
B41F023/04

US Classification:

101 33, 101 34, 101487, 101488

Abstract:

A printing device for seamless printing on a cloth is provided. A design is transferred from a print medium to the cloth. The device includes a print cylinder and a heater heating the print cylinder. The print medium is wrapped around the print cylinder, and the cloth is wrapped around the print medium. The heating of the print cylinder transfers the design to the cloth. The cloth is also seamless. The transfer of the design is done by sublimation of dye, which forms the design, induced by heating of the print cylinder. The print medium is a sublimation paper. An optional cylindrical cover is also provided. The cylindrical cover is placed around the print cylinder, and the print medium and the cloth are wrapped around the cylindrical cover.

US Patent:

7028613, Apr 18, 2006

Filed:

May 12, 2004

Appl. No.:

10/844198

Inventors:

Robert H. Kim - Gardena CA, US
Kwan B. Lee - Gardena CA, US

International Classification:

B41D 7/00
B41F 23/04

US Classification:

101 33, 101 34, 101487, 101488

Abstract:

A method of printing design seamlessly on clothing, and clothing obtained thereby are provided. The method includes steps of placing a cylindrical cover around a print cylinder, placing a print medium, on which a design is printed, around the cylindrical cover, placing a cloth around print medium, and heating the print medium so that the print medium and the cloth are heated and the design is transferred from the print medium to the cloth. The transfer of the design is done by sublimation of dye, which forms the design, induced by the step of heating. The cloth is subsequently cooled and flipped.

US Patent:

7129919, Oct 31, 2006

Filed:

Oct 31, 2003

Appl. No.:

10/697936

Inventors:

Sung Lee - Irvine CA, US
Robert Kim - Irvine CA, US
Hyuk Jegal - Seoul, KR
Sang Duk Jung - Seoul, KR

International Classification:

G09G 3/36

US Classification:

345 87, 361681

Abstract:

A flash memory broadcasting displayer panel is comprised of 1) a flash memory card, 2) an interface card, and 3) a Liquid Crystal Displayer. Time sequence type files, which are stored in the flash memory card, are processed by the interface card and transferred to the Liquid Crystal Displayer. The interface card includes a microprocessor operating with an internal BUS to control, process and route signals between the flash memory and the Liquid Crystal Displayer.

US Patent:

20220311448, Sep 29, 2022

Filed:

Jun 7, 2022

Appl. No.:

17/834922

Inventors:

- Aliso Viejo CA, US
Robert W. Kim - Aliso Viejo CA, US

Assignee:

AyDeeKay LLC dba Indie Semiconductor - Aliso Viejo CA

International Classification:

H03M 1/10

Abstract:

An analog-to-digital converter (ADC) is described. This ADC includes a conversion circuit with multiple bit-conversion circuits. During operation, the ADC may receive an input signal. Then, the conversion circuit may asynchronously perform successive-approximation-register (SAR) analog-to-digital conversion of the input signal using the bit-conversion circuits, where the bit-conversion circuits to provide a quantized representation of the input signal. For example, the bit-conversion circuits may asynchronously and sequentially perform the SAR analog-to-digital conversion to determine different bits in the quantized representation of the input signal. Moreover, the ADC may selectively perform self-calibration of a global delay of the bit-conversions circuits. Note that the timing self-calibration may be iterative and subject to a constraint that a maximum conversion time is less than a target conversion time.

US Patent:

20220216877, Jul 7, 2022

Filed:

Dec 20, 2021

Appl. No.:

17/555840

Inventors:

- Aliso Viejo CA, US
Robert W. Kim - Aliso Viejo CA, US

Assignee:

AyDeeKay LLC dba Indie Semiconductor - Aliso Viejo CA

International Classification:

H03L 7/081
H03L 7/099

Abstract:

An integrated circuit that includes a generating circuit is described. During operation, the generating circuit may provide an edge clock having a target phase within a clock period of an input clock, where the generating circuit does not include a delay-locked loop (DLL). For example, the generating circuit may include a gated ring oscillator that provides a reference clock having a first fundamental frequency that is larger than a second fundamental frequency of the input clock. Note that the gated ring oscillator may be programmable to adjust the first fundamental frequency within a predefined range of values. Moreover, the generating circuit may include a control circuit that determines a reference count of a number of edges of the reference clock within a reference period of the reference clock.

US Patent:

20220216880, Jul 7, 2022

Filed:

Jun 8, 2021

Appl. No.:

17/342526

Inventors:

- Aliso Viejo CA, US
Robert W. Kim - Aliso Viejo CA, US

Assignee:

AyDeeKay LLC dba Indie Semiconductor - Aliso Viejo CA

International Classification:

H03M 1/38
H03M 1/12

Abstract:

A conversion circuit that performs analog-to-digital conversion is described. During operation, the conversion circuit receives an input signal. Then, the conversion circuit performs analog-to-digital conversion and provides a quantized output corresponding to the input signal based at least in part on a first power-supply voltage and a second power-supply voltage of the conversion circuit. For example, the quantized output may be based at least in part on a comparison of the input signal to the first power-supply voltage and the second power-supply voltage. Moreover, the first power-supply voltage and the second power-supply voltage may specify a full-scale range of the conversion circuit. When the full-scale range exceeds a second full-scale range associated with reference voltages that are other than the first power-supply voltage and the second power-supply voltage, the quantized output may correspond to a larger number of bits than when the full-scale range equals the second full-scale range.

US Patent:

20230013568, Jan 19, 2023

Filed:

Jul 22, 2022

Appl. No.:

17/870831

Inventors:

- Aliso Viejo CA, US
Robert W. Kim - Aliso Viejo CA, US

Assignee:

AyDeeKay LLC dba Indie Semiconductor - Aliso Viejo CA

International Classification:

H03M 1/06

Abstract:

An integrated circuit may include a full-scale reference generation circuit that corrects for variation in the gain or full scale of a set of interleaved analog-to-digital converters (ADCs). Notably, the full-scale reference generation circuit may provide a given full-scale or reference setting for a given interleaved ADC, where the given full-scale setting corresponds to a predefined or fixed component and a variable component (which may specify a given full-scale correction for a given full scale). For example, the full-scale reference generation circuit may include a full-scale reference generator replica circuit that outputs a fixed current corresponding to the fixed component. Furthermore, the full-scale reference generation circuit may include a full-scale reference generator circuit that outputs a first voltage corresponding to the given full-scale setting based at least in part on the fixed current and a variable current that, at least in part, specifies the given full-scale correction.