Roger E Dufresne

US Patent:

6445021, Sep 3, 2002

Filed:

Sep 20, 2000

Appl. No.:

09/665913

Inventors:

Fen Chen - Williston VT
Roger Aime Dufresne - Fairfax VT
Baozhen Li - South Burlington VT
Alvin Wayne Strong - Essex Junction VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 27148

US Classification:

257233, 257234, 257251, 257288, 257292, 257293

Abstract:

A photodiode that exhibits a photo-induced negative differential resistance region upon biasing and illumination is described. The photodiode includes an N+ silicon substrate, a silicon nitride layer formed on the N+ silicon substrate, a reoxidized nitride layer formed on the silicon nitride layer and a N+ polysilicon layer formed on at least a portion of the reoxidized nitride layer.

US Patent:

6743655, Jun 1, 2004

Filed:

Jul 25, 2002

Appl. No.:

10/205527

Inventors:

Fen Chen - Williston VT
Roger Aime Dufresne - Fairfax VT
Baozhen Li - Burlington VT
Alvin Wayne Strong - Essex Junction VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2100

US Classification:

438 59, 438 57

Abstract:

A photodiode that exhibits a photo-induced negative differential resistance region upon biasing and illumination is described. The photodiode includes an N+ silicon substrate, a silicon nitride layer formed on the N+ silicon substrate, a reoxidized nitride layer formed on the silicon nitride layer and a N+ polysilicon layer formed on at least a portion of the reoxidized nitride layer.

US Patent:

20120187974, Jul 26, 2012

Filed:

Jan 20, 2011

Appl. No.:

13/010081

Inventors:

Roger A. Dufresne - Fairfax VT, US
Charles B. LaRow - Burlington VT, US
Travis S. Merrill - Rutland VT, US
Nilufa Rahim - Somerset NJ, US
Ernest Y. Wu - Essex Junction VT, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G01R 31/26

US Classification:

32476201

Abstract:

A testing system for testing the integrity of a gate dielectric includes a testing apparatus, the testing apparatus including a test probe configured to contact and provide a voltage across the gate dielectric and to measure a current passing through the gate dielectric. The testing system also includes a computing device coupled to the testing apparatus an causing the testing apparatus to apply a constant voltage as part of a first test to the gate dielectric through the test probe until a first predetermined current is measured passing through the gate dielectric and to apply an increasing voltage to the gate dielectric after the first predetermined current is measured.

US Patent:

20130038334, Feb 14, 2013

Filed:

Aug 11, 2011

Appl. No.:

13/207485

Inventors:

Fen Chen - Williston VT, US
Roger A. Dufresne - Fairfax VT, US
Travis S. Merrill - Rutland VT, US
Michael A. Shinosky - Jericho VT, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G01R 31/02

US Classification:

324537, 324555

Abstract:

Test structures for simultaneously testing for electromigration or stress migration fails and time dependent dielectric breakdown fails in integrated circuits, test circuits using four test structures arranged as a bridge balance circuit and methods of testing using the test circuits. The electromigration or stress migration portions of the test structures include via chains of wire segments connected in series by electrically conductive vias, the wire segments formed in at least two adjacent wiring levels of an integrated circuit. The time dependent dielectric breakdown portions of the test structures include digitized wire structures in one of the at least two adjacent wiring levels adjacent to a less than whole portion of the wire segments in the same wiring level as the digitized wire structures.

US Patent:

20130049793, Feb 28, 2013

Filed:

Aug 31, 2011

Appl. No.:

13/222306

Inventors:

Fen Chen - Williston VT, US
Roger A. Dufresne - Fairfax VT, US
Kai D. Feng - Hopewell Junction NY, US
Richard J. St-Pierre - Essex Junction VT, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G01R 31/26
G01R 31/02

US Classification:

32476203, 324537

Abstract:

A testing structure, system and method for monitoring electro-migration (EM) performance. A system is described that includes an array of testing structures, wherein each testing structure includes: an EM resistor having four point resistive measurement, wherein a first and second terminals provide current input and a third and fourth terminals provide a voltage measurement; a first transistor coupled to a first terminal of the EM resistor for supplying a test current; the voltage measurement obtained from a pair of switching transistors whose gates are controlled by a selection switch and whose drains are utilized to provide a voltage measurement across the third and fourth terminals. Also included is a decoder for selectively activating the selection switch for one of the array of testing structures; and a pair of outputs for outputting the voltage measurement of a selected testing structure.

US Patent:

20130106452, May 2, 2013

Filed:

Oct 26, 2011

Appl. No.:

13/282090

Inventors:

Fen Chen - Williston VT, US
Roger A. Dufresne - Essex Junction VT, US
Kai D. Feng - Hopewell Junction NY, US
Richard J. St-Pierre - Essex Junction VT, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G01R 31/3187

US Classification:

3247503

Abstract:

An integrated circuit, testing structure, and method for monitoring electro-migration (EM) performance. A method is described that includes method for measuring on-chip electro-migration (EM) performance, including: providing a first on-chip sensor continuously powered with a stress current; providing a second on-chip sensor that is powered only during measurement cycles with a nominal current; obtaining a first resistance measurement from the first on-chip sensor and a second resistance measurement from the second on-chip sensor during each of a series of measurement cycles; and processing the first and second resistance measurements.

US Patent:

20130191047, Jul 25, 2013

Filed:

Jan 20, 2012

Appl. No.:

13/354547

Inventors:

Fen CHEN - Williston VT, US
Roger A. DUFRESNE - Fairfax VT, US
Timothy D. SULLIVAN - Underhill VT, US
Yanfeng WANG - Fishkill NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G01R 31/26
G06F 19/00

US Classification:

702 58, 32476203

Abstract:

An on-chip poly-to-contact process monitoring and reliability evaluation system and method of use are provided. A method includes determining a breakdown electrical field of each of one or more shallow trench isolation (STI) measurement structures corresponding to respective one or more original semiconductor structures. The method further includes determining a breakdown voltage of each of one or more substrate measurement structures corresponding to the respective one or more original semiconductor structures. The method further includes determining a space between a gate and a contact of each of the one or more original semiconductor structures based on the determined breakdown electrical field and the determined breakdown voltage.

US Patent:

58987061, Apr 27, 1999

Filed:

Apr 30, 1997

Appl. No.:

8/846989

Inventors:

Roger Aime Dufresne - Fairfax VT
Charles William Griffin - Underhill VT
William Alan Klaasen - Underhill VT
Alvin Wayne Strong - Essex Junction VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 3112

US Classification:

371 28

Abstract:

The present invention is directed to an apparatus and method for reliability testing of an integrated circuit. The present invention provides a test structure and method for testing gate and node dielectrics of an integrated circuit wherein a self-heating gate structure is integrated with the product structure itself. Selected conductive lines within the product structure are used as heater elements to provide temperature stressing of the integrated circuit. The localized self-heating gate structure is an integral part of the product chip. Thus, etch and deposition characteristics of the test structure are kept identical to the etch and deposition characteristics of the product itself. As low-voltage technologies make it harder to obtain significant acceleration due to voltage stressing, temperature stressing may be used instead to increase acceleration.