Roy M Carlson

US Patent:

6791362, Sep 14, 2004

Filed:

Dec 9, 2003

Appl. No.:

10/731387

Inventors:

Roy M. Carlson - Plymouth MN
David O. Erstad - Minnetonka MN

Assignee:

Honeywell International Inc. - Morristown NJ

International Classification:

H03K 1900

US Classification:

326 93, 326 14, 326 38

Abstract:

A system and method for hardening an asynchronous combinational logic circuit against Single Event Upset (SEU) is presented. The asynchronous combinational logic circuit is located between two asynchronous registers. A fault detector is used to detect a fault at an output of the asynchronous combinational logic circuit caused by SEU. If the fault detector detects a fault, a first asynchronous register is prevented from clearing stored data and a second asynchronous register is prevented from loading data from the asynchronous combinational logic circuit until the fault is cleared. Further, a timer circuit is used to ensure enough time elapses to allow the asynchronous combinational logic circuit to reevaluate itself. The asynchronous combinational logic circuit reevaluates itself by first propagating a NULL wave front to clear the fault and then propagating the data stored in the first asynchronous register to its outputs.

US Patent:

6937053, Aug 30, 2005

Filed:

Jun 17, 2003

Appl. No.:

10/463794

Inventors:

Roy M. Carlson - Plymouth MN, US
David O. Erstad - Minnetonka MN, US

Assignee:

Honeywell International Inc. - Morristown NJ

International Classification:

H03K019/007

US Classification:

326 14, 326121, 326 93

Abstract:

A system and method for hardening a Null Convention Logic (NCL) circuit against Single Event Upset (SEU) is presented. Placing a resistive element into a feedback loop of the NCL circuit may harden the NCL circuit. A bypass element may be placed in parallel with the resistive element to increase the latching speed of the hardened NCL circuit. Additionally, replacing transistors in an input driver, the feedback loop, and an inverter with transistor stacks, which may include two or more transistors connected in series, may harden the NCL circuit. Further, two NCL gates may be cross-coupled to harden the NCL circuit.

US Patent:

7215135, May 8, 2007

Filed:

Dec 2, 2004

Appl. No.:

11/002163

Inventors:

Roy Carlson - Plymouth MN, US

Assignee:

Honeywell International Inc. - Morristown NJ

International Classification:

H03K 19/007
H03K 19/003

US Classification:

326 14, 326 13, 326 23

Abstract:

An apparatus for hardening logic circuitry against a Single-Event-Effect condition and for providing immunity to an overshoot and undershoot condition is provided. The apparatus includes undershoot-blocking and overshoot-blocking modules that are configured to be coupled to overshoot-insensitive and undershoot-insensitive nodes of the logic circuitry, respectively. The undershoot-blocking module is operable to (i) receive from a first node of the logic circuitry a first signal event having a undershoot condition impressed thereon, and (ii) block it from passing to the overshoot-insensitive node. The overshoot-blocking module is operable to (i) receive from the first node a second signal event having an overshoot condition impressed thereon, and (ii) block it from passing to the undershoot-insensitive node. As such, further propagation of the overshoot and undershoot conditions are prevented.

US Patent:

7451384, Nov 11, 2008

Filed:

Jul 15, 2004

Appl. No.:

10/891654

Inventors:

David O. Erstad - Minnetonka MN, US
Roy M. Carlson - Plymouth MN, US

Assignee:

Honeywell International Inc. - Morristown NJ

International Classification:

G06F 11/08

US Classification:

714797, 714789, 365181, 326 35

Abstract:

A system and method for providing error recovery to an asynchronous logic circuit is presented. The asynchronous logic circuit with error recovery may use temporal redundancy to compare the results of an asynchronous computation and initiate error recovery if necessary. Outputs of the asynchronous logic circuit are compared using a plurality of asynchronous register voters. If an asynchronous register voter detects an inconsistent result, the asynchronous register voter clears itself. A majority of common data outputs from the plurality of asynchronous register voters is provided as an output that is representative of the output of the asynchronous logic circuit.

US Patent:

7619455, Nov 17, 2009

Filed:

Apr 19, 2007

Appl. No.:

11/737225

Inventors:

Roy M. Carlson - Plymouth MN, US
David O. Erstad - Minnetonka MN, US

Assignee:

Honeywell International Inc. - Morristown NJ

International Classification:

H03K 3/356

US Classification:

327212, 327199, 327201

Abstract:

By adjusting a register's capturing clock edge timing so that the register captures data when the data returns to a correct state, the register may be protected against DSET upsets. If a data glitch occurs near the clock edge, the valid time at the register output is increased (CLK to Q). This valid time increase occurs when the presence of a DSET transient is detected near the clock edge.

US Patent:

8031506, Oct 4, 2011

Filed:

Mar 21, 2008

Appl. No.:

12/077888

Inventors:

Jonathan Schmitt - Eden Prairie MN, US
Roy Carlson - Plymouth MN, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G11C 17/16

US Classification:

365 96, 257530, 257209

Abstract:

A disclosed embodiment is a programmable memory cell having improved IV characteristics comprising a thick oxide spacer transistor interposed between a programmable thin oxide antifuse and a thick oxide access transistor. The spacer transistor separates a rupture site formed during programming the programmable antifuse from the access transistor, so as to result in the improved IV characteristics. The programmable antifuse is proximate to one side of the spacer transistor, while the access transistor is proximate to an opposite side of the spacer transistor. The source region of the access transistor is coupled to ground, and the drain region of the access transistor also serves as the source region of the spacer transistor. The access transistor is coupled to a row line, while the spacer transistor and the programmable antifuse are coupled to a column line. The rupture site is formed during programming by applying a programming voltage to the programmable antifuse.

US Patent:

20050156620, Jul 21, 2005

Filed:

Jan 15, 2004

Appl. No.:

10/759913

Inventors:

Roy Carlson - Plymouth MN, US

Assignee:

Honeywell International Inc. - Morristown NJ

International Classification:

H03K019/003

US Classification:

326010000

Abstract:

A system and method for hardening a logic circuit against radiation-event effects is provided. The system may include a logic circuit, first and second feed-forward devices, and first and second feedback devices. The logic circuit may be operable to output independently-obtained first and second redundant signals responsive to a desired input signal. Each of the first and second feed-forward devices may receive both of the first and second redundant signals. When the first and second redundant signals are in expected states, then the first and second feed-forward devices may responsively provide respective first and second feed-forward signals. Each of the first and second feedback devices may receive both of the first and second feed-forward signals. When the first and second feed-forward signals are in expected states, then the first and second feedback devices responsively feed respective first and second feedback signals back to the respective first and second redundant signals.

US Patent:

20060119410, Jun 8, 2006

Filed:

Dec 6, 2004

Appl. No.:

11/005265

Inventors:

Roy Carlson - Plymouth MN, US

Assignee:

Honeywell International Inc. - Morristown NJ

International Classification:

H03K 5/08

US Classification:

327310000

Abstract:

A circuit for rejecting single-event transients (SETs) from logic signals is provided. The circuit includes a delay circuit, an inverter circuit, and an output-holding circuit. The delay circuit receives an input signal and delays the input signal to produce a time-delayed version of the input signal. The input signal and the time-delayed version of the input signal are fed into the inverter circuit that propagates a corresponding output signal only when the input signal and the time-delayed version of the input signal have the same logic level. If the input signal or the time-delayed version of the input signal transitions such that both input signals presented to the inverter circuit have opposite logic levels, the output-holding circuit maintains the output signal in its previous state.