Scott Lee Irwin

US Patent:

7224951, May 29, 2007

Filed:

Sep 11, 2003

Appl. No.:

10/659966

Inventors:

Jerry Chuang - Sunnyvale CA, US
William C. Black - Ames IA, US
Scott A. Irwin - Ames IA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H04B 1/06
H04B 1/16

US Classification:

455260, 4551791, 4551803, 4551823, 455318, 455326, 375355

Abstract:

A device and a method for processing high data rate serial data includes circuitry for recovering a clock based on the high data rate input data stream. A transceiver includes a coarse loop of a phase-locked loop that selectively provides a clock having accuracy that is within a specified amount. In a sample mode of operation, only the coarse loop PLL is coupled to provide an error signal from which an oscillation signal and clock may be derived. In a second mode (lock) of operation, the transceiver may lock to the received serial data stream by coupling the fine loop PLL to provide an adjusted error signal. In a third mode of operation, (automatic) the transceiver initially performs coarse loop calibration by de-coupling the fine loop PLL and coupling the coarse loop PLL until a steady state has been reached.

US Patent:

7493095, Feb 17, 2009

Filed:

Apr 25, 2007

Appl. No.:

11/796111

Inventors:

Jerry Chuang - Sunnyvale CA, US
William C. Black - Ames IA, US
Scott A. Irwin - Ames IA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H04B 1/06
H04B 1/16

US Classification:

455260, 4551791, 4551803, 4551823, 455318, 455326, 331 16, 375221, 375355

Abstract:

A device and a method for processing high data rate serial data includes circuitry for recovering a clock based on the high data rate input data stream. A transceiver includes a coarse loop of a phase-locked loop that selectively provides a clock having accuracy that is within a specified amount. In a sample mode of operation, only the coarse loop PLL is coupled to provide an error signal from which an oscillation signal and clock may be derived. In a second mode (lock) of operation, the transceiver may lock to the received serial data stream by coupling the fine loop PLL to provide an adjusted error signal. In a third mode of operation, (automatic) the transceiver initially performs coarse loop calibration by de-coupling the fine loop PLL and coupling the coarse loop PLL until a steady state has been reached.

US Patent:

8391343, Mar 5, 2013

Filed:

Oct 7, 2008

Appl. No.:

12/247125

Inventors:

Jerry Chuang - Sunnyvale CA, US
William C. Black - Ames IA, US
Scott A. Irwin - Ames IA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H04B 1/38
H04L 27/00
H03K 9/00

US Classification:

375219, 375295, 375316

Abstract:

A high data rate transceiver for processing high data rate serial data includes circuitry for recovering a clock based on the high data rate input data stream. The transceiver includes a coarse loop of a phase-locked loop that selectively provides a clock having accuracy that is within a specified amount. In a sample mode of operation, only the coarse loop PLL is coupled to provide an error signal from which an oscillation signal and clock may be derived. In a second mode (lock) of operation, the transceiver may lock to the received serial data stream by coupling the fine loop PLL to provide an adjusted error signal. In a third mode of operation, (automatic) the transceiver initially performs coarse loop calibration by de-coupling the fine loop PLL and coupling the coarse loop PLL until a steady state has been reached.