Stephen Ray Thompson

US Patent:

8341316, Dec 25, 2012

Filed:

Nov 17, 2010

Appl. No.:

12/948677

Inventors:

David Kaplan - Austin TX, US
Christopher D. Bryant - Austin TX, US
Stephen P. Thompson - Longmont CO, US

Assignee:

Advanced Micro Devices, Inc. - Austin TX

International Classification:

G06F 3/00
G06F 9/26

US Classification:

710 55, 710 5, 711207, 719314

Abstract:

A method and apparatus are provided for controlling a translation lookaside buffer in connection with the execution of an atomic instruction. The method comprises identifying load instructions within a plurality of instructions to be executed, and placing the identified load instructions in a queue prior to execution. An atomic instruction identified in the queue is prevented from executing until the atomic instruction is the oldest instruction in the queue. The apparatus comprises a queue and a translation lookaside buffer. The queue is adapted to: identify an atomic instruction within a plurality of instructions to be executed; prevent execution of the atomic instruction until it is the oldest instruction in the queue; and send a virtual address corresponding to the atomic instruction and an atomic load signal in response to determining that the atomic instruction is the oldest instruction in the queue. The translation lookaside buffer is adapted for maintaining at least one virtual to physical address translation, and is adapted to force a miss in the translation lookaside buffer in response to receiving the atomic load signal.

US Patent:

20130346703, Dec 26, 2013

Filed:

Jun 20, 2012

Appl. No.:

13/528302

Inventors:

Donald W. McCauley - Lakeway TX, US
Stephen P. Thompson - Longmont CO, US

International Classification:

G06F 12/08

US Classification:

711137, 711E12057

Abstract:

The present invention provides a method and apparatus for throttling prefetch requests for a cache. One embodiment of the method includes selecting a sequence of relative addresses for prefetching data from a memory into lines of a cache in response to detecting a cache miss to a first address. The sequence of relative addresses is determined relative to the first address. This embodiment of the method also includes issuing a prefetch request for data from a memory address indicated by one of the sequence of relative addresses when at least one previous prefetch stream accessed prefetched data associated with this one of the sequence of relative addresses.

US Patent:

20140052927, Feb 20, 2014

Filed:

Aug 17, 2012

Appl. No.:

13/588622

Inventors:

Donald W. McCauley - Lakeway TX, US
Stephen P. Thompson - Longmont CO, US

International Classification:

G06F 12/08

US Classification:

711137, 711E12057

Abstract:

The present invention provides a method and apparatus for using prefetch hints. One embodiment of the method includes bypassing, at a first prefetcher associated with a first cache, issuing requests to prefetch data from a number of memory addresses in a sequence of memory addresses determined by the first prefetcher. The number is indicated in a request received from a second prefetcher associated with a second cache. This embodiment of the method also includes issuing, from the first prefetcher, a request to prefetch data from a memory address subsequent to the bypassed memory addresses.