Thomas Pike Alexander

US Patent:

7839854, Nov 23, 2010

Filed:

Mar 2, 2006

Appl. No.:

11/366267

Inventors:

Thomas Alexander - Palo Alto CA, US

International Classification:

H04L 12/28

US Classification:

370392, 37039531, 709242, 345503

Abstract:

The present invention provides a cost effective method to improve the performance of communication appliances by retargeting the graphics processing unit as a coprocessor to accelerate networking operations. A system and method is disclosed for using a coprocessor on a standard personal computer to accelerate packet processing operations common to network appliances. The appliances include but are not limited to routers, switches, load balancers and Unified Threat Management appliances. More specifically, the method uses common advanced graphics processor engines to accelerate the packet processing tasks.

US Patent:

7962741, Jun 14, 2011

Filed:

Sep 12, 2002

Appl. No.:

10/241478

Inventors:

Thomas Alexander - Sunnyvale CA, US
Steven Ahlgrim - Mountain View CA, US
Jing Zhang - Milpitas CA, US
Jessica Ming Chang - Sunnyvale CA, US

Assignee:

Juniper Networks, Inc. - Sunnyvale CA

International Classification:

H04L 29/06
G06F 12/14
G06F 15/16

US Classification:

713151, 713160, 713192, 726 3, 709230

Abstract:

A network device for processing data packets includes an encryption services module, a number of network interfaces and a forwarding module. A network interface receives a packet requiring encryption services and forwards the packet. The forwarding module receives at least a portion of the data packet, where the portion includes header information. The forwarding module identifies a security association for the data packet, appends the security association to the portion of the data packet and forwards the portion of the data packet including the security association to the encryption services module. The encryption services module processes the packet in accordance with the security association.

US Patent:

8077725, Dec 13, 2011

Filed:

Nov 22, 2010

Appl. No.:

12/952084

Inventors:

Thomas Alexander - Palo Alto CA, US

International Classification:

H04L 12/28

US Classification:

370392, 37039531, 709242, 345503, 726 22

Abstract:

The present invention provides a cost effective method to improve the performance of communication appliances by retargeting the graphics processing unit as a coprocessor to accelerate networking operations. A system and method is disclosed for using a coprocessor on a standard personal computer to accelerate packet processing operations common to network appliances. The appliances include but are not limited to routers, switches, load balancers and Unified Threat Management appliances. More specifically, the method uses common advanced graphics processor engines to accelerate the packet processing tasks.

US Patent:

20140052371, Feb 20, 2014

Filed:

Oct 29, 2013

Appl. No.:

14/065637

Inventors:

Joseph N. Ross - Oakland CA, US
Mark Schunder - South Lyon MI, US
Thomas Richard Alexander - Brighton MI, US
Joseph Paul Rork - Plymouth MI, US

Assignee:

Ford Global Technologies, LLC. - Dearborn MI

International Classification:

G01C 21/00

US Classification:

701465

Abstract:

A computer-implemented tracking method includes receiving a tracking request at a vehicle associated computing system (VACS). The method also includes authenticating the tracking request and determining a vehicle location via a GPS in communication with the VACS. The method further includes transmitting the vehicle location from the VACS to a tracking request associated computing system (TRACS). The method also includes monitoring the vehicle for at least one delay-event. The method additionally includes transmitting data corresponding to the delay event to the TRACS, contingent on the occurrence of at least one delay-event.

US Patent:

6301629, Oct 9, 2001

Filed:

Mar 3, 1998

Appl. No.:

9/034537

Inventors:

Bharat Sastri - Pleasanton CA
Thomas Alexander - San Jose CA
Chitranjan N. Reddy - Los Altos Hills CA

Assignee:

Alliance Semiconductor Corporation - Santa Clara CA

International Classification:

G06F 1338

US Classification:

710129

Abstract:

The present invention provides a monolithic or discrete high speed/low speed interface that is capable of interfacing with the high speed subsystems of a data processing system and low speed subsystems of a data processing system. In one embodiment, the high speed/low speed interface subsystem of the present invention comprises a high speed interface for interfacing with high speed subsystems via a high speed bus, a low speed interface for interfacing with low speed subsystems via a low speed bus, a control circuitry coupled to both the high speed and low speed interfaces, and an internal bus coupled to the control circuitry and the high speed and low speed interfaces. The control circuitry controls the transfer of information between the interfaces. In a second embodiment of the present invention, the high speed/low speed interface subsystem of the present invention comprises all the elements of the first embodiment and a prediction unit. In a third embodiment of the present invention, the high speed/low speed interface subsystem comprises all the elements of the second embodiment and a memory controller.

US Patent:

53394402, Aug 16, 1994

Filed:

Aug 21, 1992

Appl. No.:

7/933434

Inventors:

Edward M. Jacobs - Mt. View CA
Kenneth K. Chan - San Jose CA
Thomas B. Alexander - Santa Clara CA

Assignee:

Hewlett-Packard Co. - Palo Alto CA

International Classification:

G06F 1338

US Classification:

395325

Abstract:

The present invention provides a protocol method for waiting the bus in a digital computer and an apparatus for implementing that protocol. By allowing the bus to continue running after a wait command has been asserted, modules on the computer bus are not required to respond instantly to the wait command. Information on the bus during the multiple cycles of the wait period is defined as invalid and valid data is driven on the bus after the wait period has expired. Bus driver modules are provided with a replay queue to replay, on the bus, data the driver module drove on the bus during the wait period if required.

US Patent:

55242162, Jun 4, 1996

Filed:

May 13, 1994

Appl. No.:

8/242748

Inventors:

Kenneth K. Chan - San Jose CA
Thomas B. Alexander - Saratoga CA
Robert E. Naas - Fort Collins CO
Julie W. Wu - Cupertino CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1336

US Classification:

395287

Abstract:

A computer system has a multi-tiered bus system. The multi-tiered bus system includes one or more local buses and a central bus connected to each local bus by a bus interface. In order to maintain one global view of transaction ordering, the processors on each local bus record bus transactions in an order on which the bus transactions appear on the central bus. To do this, bus transactions which are initiated on any local bus are forwarded to the central bus by the corresponding bus interface. The processors connected to the local bus do not record bus transactions when they are initiated on the local bus. Every transaction which occurs on the central bus is echoed back to every local bus by the corresponding bus interface. Each processor records bus transactions at the time they are echoed back to the local bus.

US Patent:

58925163, Apr 6, 1999

Filed:

Mar 29, 1996

Appl. No.:

8/625479

Inventors:

Thomas Alexander - Santa Clara CA

Assignee:

Alliance Semiconductor Corporation - San Jose CA

International Classification:

G06T 1100

US Classification:

345430

Abstract:

A perspective texture mapping circuit (10) is disclosed. In a perspective texture mapping mode, an inverse z gradient and corresponding inverse z polygon vertex value is loaded into a first interpolator circuit (14), and texture address product gradients with corresponding polygon vertex texture address product values are loaded into a second and third interpolator circuit (16 and 18). The first interpolator circuit (14) interpolates a sequence of inverse z values for the surface of the polygon. The second and third interpolator circuits (16 and 18) interpolate corresponding texture address product values for each interpolated inverse z value. The texture address product values are divided by the corresponding inverse z value in a divider circuit (12) to generate texture address values. Texture address values are coupled to texture memory (20) to generate texel values which are passed onto an output FIFO (26). In a color interpolation mode, each pixel includes three color component.