Wei Cheng Li

US Patent:

6353691, Mar 5, 2002

Filed:

Jan 27, 2000

Appl. No.:

09/492966

Inventors:

Wei Zhong Li - San Jose CA
Yanfeng Yang - Sunnyvale CA

Assignee:

Oplink Communications, Inc. - San Jose CA

International Classification:

G02B 600

US Classification:

385 11, 385 34, 359495

Abstract:

A method and system for providing a splitter/combiner is disclosed. The splitter/combiner includes a first birefringent wedge having a first optic axis and a first wedge angle and a second birefringent wedge having a second optic axis and a second wedge angle. The second birefringent wedge is optically coupled with the first birefringent wedge. The second wedge angle is complementary to the first wedge angle. The second optic axis is perpendicular to the first optic axis such that an extraordinary signal for the first birefringent wedge is an ordinary signal for the second birefringent wedge. The first and second birefringent wedges establish a first path for a first portion of a first optical signal and establish a second path for a second portion of the first optical signal. The first path and the second path are separated by an angle. The first optical signal travels from the first birefringent wedge to the second birefringent wedge.

US Patent:

6580828, Jun 17, 2003

Filed:

Jun 30, 1999

Appl. No.:

09/343934

Inventors:

Wei Li - Cupertino CA

Assignee:

Logitech Europe, S.A. - Romanel-sur-Morges

International Classification:

G06K 936

US Classification:

382233, 382246, 708203, 341 67

Abstract:

New and improved variable length decoding methods and apparatus. The present invention provides speed performance and efficiency for decoding data by comparing, in parallel, a first plurality of code words of received data with respective values from a code length table. If the compared first plurality of code words are outside of a criterion, a second plurality of code words of received data are compared with respective values from the code length table. If one of the code words from one of the first and the second compared plurality of code words meets the criterion, it is determined which one of the code words from the first and the second compared plurality of code words has met the criterion. Once the code word meeting the criterion is determined, its symbol value is provided.

US Patent:

6591407, Jul 8, 2003

Filed:

Mar 1, 2000

Appl. No.:

09/516489

Inventors:

Douglas Kaufman - Menlo Park CA
Hazem Almusa - San Jose CA
Vinay Srinivas - Redwood City CA
Donald V. Organ - Saratoga CA
Larry Ke - San Jose CA
Wei Li - Milpitas CA
Japinder Singh - Santa Clara CA
Robert Mathews - Los Altos CA

Assignee:

Sequence Design, Inc. - Santa Clara CA

International Classification:

G06F 1750

US Classification:

716 10, 716 2, 716 3, 716 9

Abstract:

A method and an apparatus are provided for post-layout optimization of an integrated circuit. In one instance, only local transformations accomplished by incremental changes to placement and routing are provided, so as to avoid the costly design iteration loop that requires re-synthesis, re-place and re-route. Optimization can be provided in multiple optimization phases each accomplishing a specified set of transformations. Static timing analysis is performed at the end of each set of local transformations to determine if further optimization steps are required. In one instance, the physical design is first scanned for mismatch between drivers and loads. Then, in a second optimization phase, âhot spotsâ in the physical design are identified for local transformation using a âbidirectional combinational total negative slackâ (BCTNS) algorithm. In subsequent phases, optimization based on meeting setup times and hold times in a critical path are performed.

US Patent:

6721943, Apr 13, 2004

Filed:

Mar 30, 2001

Appl. No.:

09/822736

Inventors:

Rakesh Krishnaiyer - Santa Clara CA
Somnath Ghosh - San Jose CA
Wei Li - Redwood City CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 945

US Classification:

717150, 717140, 717151, 717158, 717160, 711105, 711111, 711114

Abstract:

In general, the malloc-combining transformation optimization during compile-time of a source program engaged in dynamically constructing multi-dimensional arrays provides an effective method of improving cache locality by combining qualified malloc and free/realloc calls found in counted loops into a single system call and hoisting out the single call and placing it immediately preceding the beginning of the counted loops. As a result of the application of the malloc-combining optimization results in improved cache locality allows for prefetching array pointers and data elements of the dynamic arrays as if the dynamic arrays were static.

US Patent:

6833862, Dec 21, 2004

Filed:

Jun 30, 1999

Appl. No.:

09/345167

Inventors:

Wei Li - Cupertino CA

Assignee:

Logitech, Inc. - CA

International Classification:

H04N 5225

US Classification:

34820799, 348241, 358461

Abstract:

A method and apparatus for constructing an inexpensive camera with vignetting correction in the camera electronic hardware. The hardware is programmable through the use of a register storing a constant value corresponding to the amount of vignetting of a particular lens used in the camera. The register value is provided to a correction circuit which implements an algorithm that corrects for the amount of vignetting of pixels depending upon the pixel position.

US Patent:

6995794, Feb 7, 2006

Filed:

May 18, 2001

Appl. No.:

09/861279

Inventors:

Mark Hsu - Fremont CA, US
Mitchell Norcross - Harvard MA, US
Georges Auberger - Emerald Hills CA, US
Remy Zimmermann - Belmont CA, US
Sergio Maggi - San Mateo CA, US
George Sanchez - Fremont CA, US
Bryed Billerbeck - Mountain View CA, US
Wei Li - Cupertino CA, US
Jean-Michel Junien Labrousse - Belmont CA, US

Assignee:

Logitech Europe S.A. - Romanel-sur-Morges

International Classification:

H04N 5/217
H04N 9/64

US Classification:

348241, 348243

Abstract:

A low cost camera by implementing the major functions in host software is provided. This is accomplished by sending raw, digitized data from the camera directly to the host. The increased volume of raw data is handled by either an improved compression/decompression scheme using lossless compression, using lossy compression or using a shared bus with higher bandwidth. By moving such functions as color processing and scaling to the host, the pixel correction can also be moved to the host. This in turn allows the elimination of the frame buffer memory from the camera. Finally, the camera can use a low cost lens by implementing vignetting, distortion, gamma or aliasing correction with a correction value stored in a register of the camera for later access by the host to perform corrections.

US Patent:

7155446, Dec 26, 2006

Filed:

Jun 14, 2004

Appl. No.:

10/867923

Inventors:

Thierry Cruanes - Redwood City CA, US
Wei Li - San Carlos CA, US
Ari Mozes - Lexington MA, US
Benoit Dageville - Foster City CA, US

Assignee:

Oracle International Corporation - Redwood Shores CA

International Classification:

G06F 17/00

US Classification:

707101, 708320, 712 1

Abstract:

A method and apparatus for performing recursive database operations is provided. According to one aspect, a plurality of first-stage slaves and a plurality of second-stage slaves are established in a database server. During one or more iterations of a recursive database operation, the first-stage slaves concurrently process data items stored in a data repository and send results to the second-stage slaves. The second-stage slaves receive the results and concurrently process those results. The second-stage slaves store the results of the second-stage slaves' processing in the data repository. Subsequent iterations of the recursive database operation proceed in this manner until the recursive database operation has been completed. In each iteration, the first-stage slaves consume the product of the second-stage slaves' previous iteration's processing, and the second-stage slaves consume the product of the first-stage slaves' current iteration's processing.

US Patent:

7155575, Dec 26, 2006

Filed:

Dec 18, 2002

Appl. No.:

10/323226

Inventors:

Rakesh Krishnaiyer - Santa Clara CA, US
Wei Li - Redwood City CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/08

US Classification:

711137, 711169, 712207

Abstract:

A computer program product determines whether a loop has a high usage count. If the computer program product determines the loop has a high usage count, the computer program product determines whether the loop has an irregularly accessed load. If the loop has an irregularly accessed load, the computer program product inserts pattern recognition code to calculate whether successive iterations of the irregular memory load in the loop have a predictable access pattern. The computer program product implants conditional adaptive prefetch code including a prefetch instruction into the output code.