Yan Zhang Li

US Patent:

6771536, Aug 3, 2004

Filed:

Feb 27, 2002

Appl. No.:

10/086495

Inventors:

Yan Li - Milpitas CA
Jian Chen - San Jose CA

Assignee:

SanDisk Corporation - Sunnyvale CA

International Classification:

G11C 1604

US Classification:

36518502, 36518511, 36518518, 36518527, 36518529

Abstract:

The present invention presents a non-volatile memory having a plurality of erase units or blocks, where each block is divided into a plurality of parts sharing the same word lines to save on the row decoder area, but which can be read or programmed independently. An exemplary embodiment is a Flash EEPROM memory with a NAND architecture that has blocks composed of a left half and a right half, where each part will accommodate one or more standard page (data transfer unit) sizes of 512 bytes of data. In the exemplary embodiment, the left and right portions of a block each have separate source lines, and separate sets of source and drain select lines. During the programming or reading of the left side, as an example, the right side can be biased to produce channel boosting to reduce data disturbs. In an alternate set of embodiments, the parts can have separate well structures.

US Patent:

6987693, Jan 17, 2006

Filed:

Sep 24, 2002

Appl. No.:

10/254290

Inventors:

Yan Li - Milpitas CA, US

Assignee:

SanDisk Corporation - Sunnyvale CA

International Classification:

G11C 11/34

US Classification:

36518512, 36518511

Abstract:

A memory device and a method thereof allow programming and sensing a plurality of memory cells in parallel in order to minimize errors caused by coupling from fields of neighboring cells and to improve performance. The memory device and method have the plurality of memory cells linked by the same word line and a read/write circuit is coupled to each memory cells in a contiguous manner. Thus, a memory cell and its neighbors are programmed together and the field environment for each memory cell relative to its neighbors during programming and subsequent reading is less varying. This improves performance and reduces errors caused by coupling from fields of neighboring cells, as compared to conventional architectures and methods in which cells on even columns are programmed independently of cells in odd columns.

US Patent:

6996003, Feb 7, 2006

Filed:

Jun 14, 2004

Appl. No.:

10/868728

Inventors:

Yan Li - Milpitas CA, US
Jian Chen - San Jose CA, US

Assignee:

SanDisk Corporation - Sunnyvale CA

International Classification:

G11C 16/04

US Classification:

36518502, 36518511, 36518518, 36518527, 36518529

Abstract:

The present invention presents a non-volatile memory having a plurality of erase units or blocks, where each block is divided into a plurality of parts sharing the same word lines to save on the row decoder area, but which can be read or programmed independently. An exemplary embodiment is a Flash EEPROM memory with a NAND architecture that has blocks composed of a left half and a right half, where each part will accommodate one or more standard page (data transfer unit) sizes of 512 bytes of data. In the exemplary embodiment, the left and right portions of a block each have separate source lines, and separate sets of source and drain select lines. During the programming or reading of the left side, as an example, the right side can be biased to produce channel boosting to reduce data disturbs. In an alternate set of embodiments, the parts can have separate well structures.

US Patent:

7023736, Apr 4, 2006

Filed:

Sep 17, 2003

Appl. No.:

10/665828

Inventors:

Yan Li - Milpitas CA, US

Assignee:

SanDisk Corporation - Sunnyvale CA

International Classification:

G11C 16/06

US Classification:

36518521, 365205, 365203

Abstract:

A method for reducing source line bias is accomplished by read/write circuits with features and techniques for multi-pass sensing. When a page of memory cells are being sensed in parallel, each pass helps to identify and shut down the memory cells with conduction current higher than a given demarcation current value. In particular, the identified memory cells are shut down after all sensing in the current pass have been completed. In this way the shutting down operation does not disturb the sensing operation. Sensing in subsequent passes will be less affected by source line bias since the total amount of current flow is significantly reduced by eliminating contributions from the higher current cells. In another aspect of sensing improvement, a reference sense amplifier is employed to control multiple sense amplifiers to reduce their dependence on power supply and environmental variations.

US Patent:

7057939, Jun 6, 2006

Filed:

Apr 23, 2004

Appl. No.:

10/830824

Inventors:

Yan Li - Milpitas CA, US
Yupin Kawing Fong - Fremont CA, US
Toru Miwa - Kanagawa, JP

Assignee:

SanDisk Corporation - Sunnyvale CA

International Classification:

G11C 16/04

US Classification:

36518528, 36518518, 36518503

Abstract:

In a non-volatile memory programming scheme where the memory cells are programmed in two or more sequential programming passes, when there is insufficient host data to program at least some of the memory cells during the second pass, some of the memory cells may be programmed to the wrong threshold voltage. This can be prevented by modifying the programming scheme so that this does not occur. In one implementation, this is accomplished by choosing a code scheme, which does not cause the memory cells to be programmed to the wrong threshold voltage during the second programming pass, or by programming the memory cells in accordance with substitute data that would not cause the cells to be programmed to an erroneous state.

US Patent:

7064980, Jun 20, 2006

Filed:

Sep 17, 2003

Appl. No.:

10/667222

Inventors:

Yan Li - Milpitas CA, US
Mehrdad Mofidi - Fremont CA, US
Shahzad Khalid - West Los Angeles CA, US

Assignee:

SanDisk Corporation - Sunnyvale CA

International Classification:

G11C 16/04

US Classification:

36518511, 36518517, 36518518

Abstract:

When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention provides as part of a programming circuit and method in which an offset to the perturbation is added to the adjacent memory storage unit still under programming. The offset is added by a controlled coupling between the adjacent bit lines of the program-inhibited memory storage unit and the still under programming memory storage unit. In this way, an error inherent in programming in parallel high-density memory storage units is eliminated or minimized.

US Patent:

7110298, Sep 19, 2006

Filed:

Jul 20, 2004

Appl. No.:

10/896096

Inventors:

Farookh Moogat - Fremont CA, US
Yan Li - Milpitas CA, US
Alexander K. Mak - Los Altos CA, US

Assignee:

SanDisk Corporation - Sunnyvale CA

International Classification:

G11C 16/04

US Classification:

36518518, 36518519, 3651852

Abstract:

In a non-volatile memory system, when it is discovered that the voltage pump pulse provided by a charge pump for programming the memory cells does not match a reference voltage, the programming time period of the voltage pump pulse is adjusted to a value that remains substantially unchanged until the end of the programming cycle. In this manner, the fluctuation in the effective programming time period of the programming pulses is prevented for the remainder of the programming cycle so that a broadening of the threshold voltage distribution will not occur or will be reduced. This feature allows a short programming time period to be designated for the programming pulses for enhanced performance, while allowing the flexibility of increased program time period when the charge pump is operating under conditions that causes it to be slow and/or weak.

US Patent:

7120051, Oct 10, 2006

Filed:

Dec 14, 2004

Appl. No.:

11/013125

Inventors:

Sergey Anatolievich Gorobets - Edinburgh, GB
Yan Li - Milpitas CA, US

Assignee:

SanDisk Corporation - Milpitas CA

International Classification:

G11C 11/34
G11C 16/04

US Classification:

36518502, 36518512, 36518517, 36518503, 36518522

Abstract:

The present invention presents techniques whereby a memory system interrupts a programming process and restarts it including additional data. More specifically, when a memory system programs data into a group of cells together as programming unit, programming can begin with less than the full data content which the group can hold. In one embodiment, the present invention allows overlapped programming of upper and lower data pages, where once the memory begins programming the lower logical data page, if data is received for the upper page assigned to the same physical page, programming is interrupted and recommenced with the concurrent programming of both the upper and the loser pages. In a complimentary embodiment, when a page contains multiple sectors of data, programming of the physical page can begin when one or more, but less than all, of the sectors forming the corresponding logical page have been received, stopped and restarted to include additional sectors of the page.