Yi Fang Wu

US Patent:

7487488, Feb 3, 2009

Filed:

Oct 6, 2006

Appl. No.:

11/544105

Inventors:

Dajen Huang - Sunnyvale CA, US
Yi Wu - Santa Clara CA, US
Arjun Dutt - Santa Clara CA, US
Yu L. Zheng - Fremont CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 17/50

US Classification:

716 14, 716 10

Abstract:

A mechanism is disclosed for assigning repeaters to signal paths in an integrated circuit design. The mechanism involves reserving, in a first metal layer of the integrated circuit design, metal tracks for routing signals. Access points to a plurality of repeaters are reserved in a second metal layer of the integrated circuit design. Each access point is associated with a particular repeater. The design may have other layers between the second metal layer and a region reserved for the repeaters. The number of repeaters may be based on the number of metal tracks that are available to route signals through the first region. Signal paths are assigned routes that comprise at least a portion of one or more of the metal tracks. A route from signal paths requiring a repeater to access points to a particular repeater is determined. Thus, the signal paths are assigned to a repeater.

US Patent:

7519933, Apr 14, 2009

Filed:

Sep 21, 2006

Appl. No.:

11/524820

Inventors:

Arjun Dutt - Mountain View CA, US
Dajen Huang - Sunnyvale CA, US
Yi Wu - Mountain View CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 17/50

US Classification:

716 10, 716 9

Abstract:

A method for inserting repeaters in an integrated circuit includes establishing a set of initial constraints for a given set of buses; assigning at least one repeater corresponding to each of the given set of buses based on the set of initial constraints; progressively relaxing the set of initial constraints to form a new set of constraints for a new set of buses and assigning at least one repeater corresponding to each of the new set of buses based on the new set of constraints; and routing assigned repeaters to each of the new set of buses in the integrated circuit.

US Patent:

7577933, Aug 18, 2009

Filed:

Nov 17, 2006

Appl. No.:

11/601148

Inventors:

Yi Wu - Santa Clara CA, US
Kenan Yu - San Jose CA, US
James G. Ballard - Palo Alto CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 17/50

US Classification:

716 13, 716 9, 716 10, 716 14, 716 6

Abstract:

A mechanism is disclosed for determining pin assignments in an integrated circuit. More particularly, the mechanism involves accessing design information for the integrated circuit. The design information includes a floorplan that sets forth an arrangement of blocks in the integrated circuit and timing information for interconnections between the blocks. Based on the timing information, routing information is determined for the interconnections between the blocks. The routing information includes physical routes and physical pin placements for the interconnections.

US Patent:

7836422, Nov 16, 2010

Filed:

May 15, 2008

Appl. No.:

12/121514

Inventors:

Dajen Huang - Santa Clara CA, US
Yi Wu - Santa Clara CA, US

Assignee:

Oracle America, Inc. - Redwood City CA

International Classification:

G06F 17/50

US Classification:

716 13, 716 12, 716 14, 257207

Abstract:

A method for routing wires in an integrated circuit includes defining an even number n of initial width routing tracks in a selected routing channel. The n initial routing tracks are separated by a substantially equal first separation distance from the other routing tracks, Vss and Vdd in the routing channel. The n initial width routing tracks and the first separation distance have an initial width about equal to the minimum design width. An odd number of routing tracks less than n are then selected, the odd number of routing tracks have a second pitch greater than the first pitch, assigning the odd number of routing tracks in the routing channel. A third routing pitch can be defined that is wider than the second routing pitch for alternating routing tracks at the odd number of routing tracks if needed. A wire routing system in an integrated circuit is also described.

US Patent:

7840076, Nov 23, 2010

Filed:

Nov 22, 2006

Appl. No.:

11/604114

Inventors:

Jean-Yves Bouguet - Belmont CA, US
Carole Dulong - Saratoga CA, US
Igor V. Kozintsev - San Jose CA, US
Yi Wu - San Jose CA, US
Ara V. Nefian - Palo Alto CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06K 9/62

US Classification:

382224

Abstract:

An image retrieval program (IRP) may be used to query a collection of digital images. The IRP may include a mining module to use local and global feature descriptors to automatically rank the digital images in the collection with respect to similarity to a user-selected positive example. Each local feature descriptor may represent a portion of an image based on a division of that image into multiple portions. Each global feature descriptor may represent an image as a whole. A user interface module of the IRP may receive input that identifies an image as the positive example. The user interface module may also present images from the collection in a user interface in a ranked order with respect to similarity to the positive example, based on results of the mining module. Query concepts may be saved and reused. Other embodiments are described and claimed.

US Patent:

7917878, Mar 29, 2011

Filed:

Jan 30, 2008

Appl. No.:

12/022950

Inventors:

Dajen Huang - Sunnyvale CA, US
Yi Wu - Santa Clara CA, US
Robert R. Brown - Fremont CA, US

Assignee:

Oracle America, Inc. - Redwood City CA

International Classification:

G06F 17/50

US Classification:

716119, 716120, 716123, 716124, 716125, 716126

Abstract:

A number of virtual regionalization lines are laid out across a chip such that the virtual regionalization lines delineate a plurality of regions on the chip. One of the plurality of regions on the chip is designated as a master region and each of a remainder of the plurality of regions on the chip is designated as a duplicate region. A number of functional blocks are placed in the master region. Each of the functional blocks is replicated in each duplicate region by placing each functional block in each duplicate region so as to be symmetric with the corresponding functional block in the master region about the virtual regionalization lines. Wires are routed in the master region. The wires routed in the master region are replicated in each duplicate region so as to be symmetric about the virtual regionalization lines.

US Patent:

8091058, Jan 3, 2012

Filed:

Nov 26, 2008

Appl. No.:

12/324439

Inventors:

James G. Ballard - Palo Alto CA, US
Yi Wu - Santa Clara CA, US

Assignee:

Oracle America, Inc. - Redwood City CA

International Classification:

G06F 17/50

US Classification:

716114, 716104, 716105, 716118, 716120, 716124, 716125, 716130, 716131, 716133

Abstract:

A method of performing a pre-route repeater insertion methodology for at least part of a circuit design may include: partitioning at least part of a circuit design into a plurality of tiles; determining at least one attribute of one or more individual tiles of the plurality of tiles; and determining a repeater solution based at least in part on the determined attributes of the one or more individual tiles. A computer implemented tool for performing a pre-route repeater insertion methodology for at least part of a circuit design may include: a module configured to partition at least part of a circuit design into a plurality of tiles; a module configured to determine at least one attribute of one or more individual tiles of the plurality of tiles; and a module configured to determine a repeater solution based at least in part on the determined attributes of the one or more individual tiles.

US Patent:

8099701, Jan 17, 2012

Filed:

Feb 27, 2009

Appl. No.:

12/395444

Inventors:

Dajen Huang - Santa Clara CA, US
Yi Wu - Santa Clara CA, US
Robert R. Brown - Santa Clara CA, US

Assignee:

Oracle America, Inc. - Redwood City CA

International Classification:

G06F 17/50

US Classification:

716126, 716125, 716139

Abstract:

Methods and apparatuses are disclosed for improving the speed of chip routing for integrated circuit blocks with multiple connections. In some embodiments, the method may include creating a layout abstract for a first block and a second block of the integrated circuit, where the first and second blocks are coupled together via a plurality of connections. The method may further include determining whether the number of connections in the plurality exceeds a threshold, and in the event that the number of connections exceeds the predetermined threshold, representing a first subset of the plurality as a first logical connection.