Yiming Li

US Patent:

20100314725, Dec 16, 2010

Filed:

Jun 12, 2009

Appl. No.:

12/483759

Inventors:

Shiqun Gu - San Diego CA, US
Arvind Chandrasekaran - San Diego CA, US
Urmi Ray - Ramona CA, US
Yiming Li - San Diego CA, US

Assignee:

QUALCOMM INCORPORATED - San Diego CA

International Classification:

H01L 23/00
H01L 21/306
H01L 21/31

US Classification:

257635, 257632, 438700, 438778, 257E23002, 257E21215, 257E2124

Abstract:

A semiconductor component (such as a semiconductor wafer or semiconductor die) includes a substrate having a front side and a back side. The semiconductor die/wafer also includes a stress balance layer on the back side of the substrate. An active layer deposited on the front side of the substrate creates an unbalanced stress in the semiconductor wafer/die. The stress balance layer balances stress in the semiconductor wafer/die. The stress in the stress balance layer approximately equals the stress in the active layer. Balancing stress in the semiconductor component prevents warpage of the semiconductor wafer/die.

US Patent:

20110012239, Jan 20, 2011

Filed:

Apr 12, 2010

Appl. No.:

12/758311

Inventors:

Shiqun Gu - San Diego CA, US
Urmi Ray - San Diego CA, US
Yiming Li - San Diego CA, US
Arvind Chandrasekaran - San Diego CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

H01L 29/06
H01L 21/768
H01L 21/311

US Classification:

257637, 438618, 438613, 438694, 257E29007, 257E21584, 257E21589, 257E21249

Abstract:

A barrier layer deposited on the passivation layer of a semiconductor die decreases adhesion of glue used during stacking of semiconductor dies by altering chemical or structural properties of the passivation layer. During detachment of a carrier wafer from a wafer, the barrier layer reduces glue residue on the wafer by modifying the surface of the passivation layer. The barrier layer may be insulating films such as silicon dioxide, silicon nitride, silicon carbide, polytetrafluoroethylene, organic layers, or epoxy and may be less than two micrometers in thickness. Additionally, the barrier layer may be used to reduce topography of the semiconductor die to decrease adhesion of glues.

US Patent:

20110204517, Aug 25, 2011

Filed:

Feb 23, 2010

Appl. No.:

12/710399

Inventors:

Shiqun Gu - San Diego CA, US
Yiming Li - San Diego CA, US
Steve J. Bezuk - San Diego CA, US

Assignee:

QUALCOMM INCORPORATED - San Diego CA

International Classification:

H01L 23/48
H01L 21/768
H01L 21/50

US Classification:

257751, 438653, 438107, 257E23011, 257E21597, 257E21499

Abstract:

A semiconductor die includes a via within a substrate material of the semiconductor die. The via includes a first conductive material having a first Coefficient of Thermal Expansion (CTE) and a second conductive material between the first conductive material and the substrate material of the semiconductor die. The second conductive material has a second CTE between the first CTE and a CTE of the substrate material of the semiconductor die. The first conductive material can be copper. The second conductive material can be tungsten and/or nickel. The substrate material can be silicon.

US Patent:

20110229687, Sep 22, 2011

Filed:

Mar 19, 2010

Appl. No.:

12/727775

Inventors:

Shiqun Gu - San Diego CA, US
Xia Li - San Diego CA, US
Yiming Li - San Diego CA, US

Assignee:

QUALCOMM INCORPORATED - San Diego CA

International Classification:

B32B 3/10
B44C 1/22

US Classification:

428131, 216 41

Abstract:

Fabrication of a through glass via in a relatively thick glass substrate includes patterning a through glass via hard mask on a surface of the glass substrate. The fabrication also includes wet etching a portion of the glass substrate, through the hard mask, to create a partial through glass via. The wet etching may involve applying a vapor of an oxide etch chemical, such as HF and XeF6, or applying a wet oxide etch chemical, such as HF and XeF6. The fabrication further includes passivating the etched partial through glass via, removing bottom passivation from the partial through glass via, and repeating the etching, passivating and removing to create the through glass via. The resulting through glass via has a scalloped side wall, a vertical profile and a high aspect ratio.

US Patent:

20110248405, Oct 13, 2011

Filed:

Apr 9, 2010

Appl. No.:

12/757570

Inventors:

Yiming Li - San Diego CA, US
Mario Francisco Velez - San Diego CA, US
Shiqun Gu - San Diego CA, US

Assignee:

QUALCOMM INCORPORATED - San Diego CA

International Classification:

H01L 23/48
H01L 21/768

US Classification:

257773, 438667, 257E21597, 257E23011

Abstract:

A block layer deposited on a substrate before deposition of metal lines and etching of a through via enables low cost fabrication of through vias in a substrate using isotropic etching processes. For example, wet etching of a glass substrate may be used to fabricate through glass vias without undercut from the wet etching shorting metal lines on the glass substrate. The block layer prevents contact between a conductive layer lining the through via with more than one metal line on the substrate. The manufacturing process allows stacking of devices on substrates such as glass substrates and connecting the devices with through vias.

US Patent:

20120248582, Oct 4, 2012

Filed:

Apr 1, 2011

Appl. No.:

13/078672

Inventors:

Shiqun Gu - San Diego CA, US
Ratibor Radojcic - San Diego CA, US
Yiming Li - Cupertino CA, US

Assignee:

QUALCOMM INCORPORATED - San Diego CA

International Classification:

H01L 23/58
H01L 21/50
H01L 21/31

US Classification:

257632, 438758, 438106

Abstract:

A voltage-switchable dielectric layer may be employed on a die for electrostatic discharge (ESD) protection. The voltage-switchable dielectric layer functions as a dielectric layer between terminals of the die during normal operation of the die. When ESD events occur at the terminals of the die, a high voltage between the terminals switches the voltage-switchable dielectric layer into a conducting layer to allow current to discharge to a ground terminal of the die without the current passing through circuitry of the die. Thus, damage to the circuitry of the die is reduced or prevented during ESD events on dies with the voltage-switchable dielectric layer. The voltage-switchable dielectric layer may be deposited on the back side of a die for protection during stacking with a second die to form a stacked IC.

US Patent:

20130316526, Nov 28, 2013

Filed:

Aug 1, 2013

Appl. No.:

13/956703

Inventors:

Ratibor Radojcic - San Diego CA, US
Yiming Li - Cupertino CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

H01L 23/62

US Classification:

438601

Abstract:

A voltage-switchable dielectric layer may be employed on a die for electrostatic discharge (ESD) protection. The voltage-switchable dielectric layer functions as a dielectric layer between terminals of the die during normal operation of the die. When ESD events occur at the terminals of the die, a high voltage between the terminals switches the voltage-switchable dielectric layer into a conducting layer to allow current to discharge to a ground terminal of the die without the current passing through circuitry of the die. Thus, damage to the circuitry of the die is reduced or prevented during ESD events on dies with the voltage-switchable dielectric layer. The voltage-switchable dielectric layer may be deposited on the back side of a die for protection during stacking with a second die to form a stacked IC. A method includes depositing a voltage-switchable dielectric layer on a first die between a first terminal and a second terminal.

US Patent:

20220365942, Nov 17, 2022

Filed:

Aug 1, 2022

Appl. No.:

17/816529

Inventors:

- Mountain View CA, US
Chen Ding - Redwood City CA, US
David Francois Huynh - San Francisco CA, US
JinYu Lou - Shanghai, CN
Yanlai Huang - Shanghai, CN
Hongda Shen - Sunnyvale CA, US
Guanghua Li - Shanghai, CN
Yiming Li - Gainesville FL, US
Yangyang Chai - Shanghai, CN

International Classification:

G06F 16/2457
G06F 16/248
G06F 16/951
G06F 16/901
G06F 16/9038
G06F 16/2452

Abstract:

Methods and systems are provided for ranking search results and generating a presentation. In some implementations, a search system generates a presentation based on a search query. In some implementations, a search system ranks search results based on data stored in a knowledge graph. In some implementations, a search system identifies a modifying concept such as a superlative in a received search query, and determines ranking properties based on the modifying concept.