Allen W Ko

US Patent:

20190185996, Jun 20, 2019

Filed:

Feb 6, 2019

Appl. No.:

16/269337

Inventors:

- Santa Clara CA, US
Allen KO - Fremont CA, US
Xinhai HAN - Santa Clara CA, US
Thomas Jongwan KWON - Dublin CA, US
Bok Hoen KIM - San Jose CA, US
Byung Ho KIL - Gangdong-gu, KR
Ryeun KIM - Wonju-Si, KR
Sang Hyuk KIM - Gyeonggi, KR

International Classification:

C23C 16/34
H01L 21/02
H01L 21/311
C23C 16/455
C23C 16/40

Abstract:

The present disclosure generally relate to thin films incorporating high aspect ratio feature definitions and methods for forming the same. As gate height increases, 3D NAND gate stacks are subject to higher aspect ratio etching. Due to the current limitations of etching techniques, the vertical etch profile typically tapers as the depth into the gate stack increases. The inventors have devised a unique deposition scheme that compensates for etch performance degradation in deep trenches by a novel plasma-enhanced chemical vapor deposition (PECVD) film deposition method. The inventors have found that by grading various properties (e.g., refractive index, stress of the film, dopant concentration in the film) of the as-deposited films (e.g., silicon nitride) a more uniform etch profile can be achieved by compensating for variations in both dry and wet etch rates.

US Patent:

20170162417, Jun 8, 2017

Filed:

Dec 6, 2016

Appl. No.:

15/370682

Inventors:

- Santa Clara CA, US
Hiroji HANAWA - Sunnyvale CA, US
Juan Carlos ROCHA-ALVAREZ - San Carlos CA, US
Pramit MANNA - Sunnyvale CA, US
Michael Wenyoung TSIANG - Fremont CA, US
Allen KO - Fremont CA, US
Wenjiao WANG - Sunnyvale CA, US
Yongjing LIN - San Jose CA, US
Prashant Kumar KULSHRESHTHA - San Jose CA, US
Xinhai HAN - Santa Clara CA, US
Bok Hoen KIM - San Jose CA, US
Kwangduk Douglas LEE - Redwood City CA, US
Karthik Thimmavajjula NARASIMHA - San Francisco CA, US
Ziqing DUAN - Sunnyvale CA, US
Deenesh PADHI - Sunnyvale CA, US

International Classification:

H01L 21/683
C23C 16/505
C23C 16/458

Abstract:

Techniques are disclosed for methods and apparatuses of an electrostatic chuck suitable for operating at high operating temperatures. In one example, a substrate support assembly is provided. The substrate support assembly includes a substantially disk-shaped ceramic body having an upper surface, a cylindrical sidewall, and a lower surface. The upper surface is configured to support a substrate thereon for processing the substrate in a vacuum processing chamber. The cylindrical sidewall defines an outer diameter of the ceramic body. The lower surface is disposed opposite the upper surface. An electrode is disposed in the ceramic body. A circuit is electrically connected to the electrode. The circuit includes a DC chucking circuit, a first RF drive circuit, and a second RF dive circuit. The DC chucking circuit, the first RF drive circuit and the second RF drive circuit are electrically coupled with the electrode.

US Patent:

20160322200, Nov 3, 2016

Filed:

Apr 29, 2016

Appl. No.:

15/142022

Inventors:

- Santa Clara CA, US
Xinhai HAN - Santa Clara CA, US
Praket P. JHA - San Jose CA, US
Masaki OGATA - San Jose CA, US
Zhijun JIANG - Sunnyvale CA, US
Allen KO - Fremont CA, US
Ndanka O. MUKUTI - Santa Clara CA, US
Thuy BRITCHER - San Jose CA, US
Amit Kumar BANSAL - Sunnyvale CA, US
Ganesh BALASUBRAMANIAN - Sunnyvale CA, US
Juan Carlos ROCHA-ALVAREZ - San Carlos CA, US
Bok Hoen KIM - San Jose CA, US

International Classification:

H01J 37/32
C23C 16/509
C23C 16/455

Abstract:

A method and apparatus for a dual-channel showerhead is provided. In one embodiment the showerhead comprises a body comprising a conductive material having a plurality of first openings formed therethrough comprising a first gas channel and a plurality of second openings formed therethrough comprising a second gas channel that is fluidly separated from the first gas channel, wherein each of the first openings having a geometry that is different than each of the second openings.

US Patent:

20160293609, Oct 6, 2016

Filed:

Mar 8, 2016

Appl. No.:

15/063569

Inventors:

- Santa Clara CA, US
Allen KO - Fremont CA, US
Xinhai HAN - Santa Clara CA, US
Thomas Jongwan KWON - Dublin CA, US
Bok Hoen KIM - San Jose CA, US
Byung Ho KIL - Gangdong-gu, KR
Ryeun KIM - Wonju-Si, KR
Sang Hyuk KIM - Gyeonggi, KR

International Classification:

H01L 27/115
H01L 21/311
C23C 16/455
C23C 16/40
C23C 16/34
H01L 29/423
H01L 21/02

Abstract:

Implementations of the present disclosure generally relate to thin films incorporating high aspect ratio feature definitions and methods for forming the same. As gate height increases, D NAND gate stacks are subject to higher aspect ratio etching. Due to the current limitations of etching techniques, the vertical etch profile typically tapers as the depth into the gate stack increases. The inventors have devised a unique deposition scheme that compensates for etch performance degradation in deep trenches by a novel plasma-enhanced chemical vapor deposition (PECVD) film deposition method. The inventors have found that by grading various properties (e.g., refractive index, stress of the film, dopant concentration in the film) of the as-deposited films (e.g., silicon nitride) a more uniform etch profile can be achieved by compensating for variations in both dry and wet etch rates.