Allen C Ko

US Patent:

20190185996, Jun 20, 2019

Filed:

Feb 6, 2019

Appl. No.:

16/269337

Inventors:

- Santa Clara CA, US
Allen KO - Fremont CA, US
Xinhai HAN - Santa Clara CA, US
Thomas Jongwan KWON - Dublin CA, US
Bok Hoen KIM - San Jose CA, US
Byung Ho KIL - Gangdong-gu, KR
Ryeun KIM - Wonju-Si, KR
Sang Hyuk KIM - Gyeonggi, KR

International Classification:

C23C 16/34
H01L 21/02
H01L 21/311
C23C 16/455
C23C 16/40

Abstract:

The present disclosure generally relate to thin films incorporating high aspect ratio feature definitions and methods for forming the same. As gate height increases, 3D NAND gate stacks are subject to higher aspect ratio etching. Due to the current limitations of etching techniques, the vertical etch profile typically tapers as the depth into the gate stack increases. The inventors have devised a unique deposition scheme that compensates for etch performance degradation in deep trenches by a novel plasma-enhanced chemical vapor deposition (PECVD) film deposition method. The inventors have found that by grading various properties (e.g., refractive index, stress of the film, dopant concentration in the film) of the as-deposited films (e.g., silicon nitride) a more uniform etch profile can be achieved by compensating for variations in both dry and wet etch rates.

US Patent:

20160293609, Oct 6, 2016

Filed:

Mar 8, 2016

Appl. No.:

15/063569

Inventors:

- Santa Clara CA, US
Allen KO - Fremont CA, US
Xinhai HAN - Santa Clara CA, US
Thomas Jongwan KWON - Dublin CA, US
Bok Hoen KIM - San Jose CA, US
Byung Ho KIL - Gangdong-gu, KR
Ryeun KIM - Wonju-Si, KR
Sang Hyuk KIM - Gyeonggi, KR

International Classification:

H01L 27/115
H01L 21/311
C23C 16/455
C23C 16/40
C23C 16/34
H01L 29/423
H01L 21/02

Abstract:

Implementations of the present disclosure generally relate to thin films incorporating high aspect ratio feature definitions and methods for forming the same. As gate height increases, D NAND gate stacks are subject to higher aspect ratio etching. Due to the current limitations of etching techniques, the vertical etch profile typically tapers as the depth into the gate stack increases. The inventors have devised a unique deposition scheme that compensates for etch performance degradation in deep trenches by a novel plasma-enhanced chemical vapor deposition (PECVD) film deposition method. The inventors have found that by grading various properties (e.g., refractive index, stress of the film, dopant concentration in the film) of the as-deposited films (e.g., silicon nitride) a more uniform etch profile can be achieved by compensating for variations in both dry and wet etch rates.