Andy Xi Liu

US Patent:

7224671, May 29, 2007

Filed:

Aug 15, 2001

Appl. No.:

09/930764

Inventors:

Eugene Lee - San Jose CA, US
Somsubhra Sikdar - San Jose CA, US
Andy Liu - Fremont CA, US
Ann Gui - Cupertino CA, US

Assignee:

Force10 Networks, Inc. - San Jose CA

International Classification:

G08C 15/00
H04J 3/14
H04L 12/26
H04L 12/28
H04L 12/56

US Classification:

370235, 370422

Abstract:

A data rate controller controls a rate that data is transferred over a backplane in a network processing device. A bandwidth allocator allocates bandwidth to an input port for transmitting data over the backplane to an output port. A bandwidth limiter identifies a maximum allowable bandwidth the input port is allocated on the backplane. A bandwidth tracker identifies an amount of bandwidth currently allocated to the input port for transmitting data over the backplane to the output port. When the current allocated bandwidth is used up, the data rate controller prevents that input port from connecting to output ports through the backplane until more bandwidth is allocated.

US Patent:

7586927, Sep 8, 2009

Filed:

Nov 4, 2003

Appl. No.:

10/704218

Inventors:

Andy Liu - Fremont CA, US
Ann Gui - Cupertino CA, US

Assignee:

Force 10 Networks, Inc. - San Jose CA

International Classification:

H04L 12/28

US Classification:

370408, 370447, 370461

Abstract:

Multiple comparators compare the enable and priority values for multiple inputs and select a winner from one of the inputs. Multiple comparator stages each include one or more of the comparators. Each comparator stage selects winners from the outputs of a preceding comparator stage. The overall winners are those inputs that are winners in each comparator stage. If there are multiple overall winners, a second arbitration is preformed to identify an ultimate winner.

US Patent:

57686173, Jun 16, 1998

Filed:

Nov 17, 1993

Appl. No.:

8/153560

Inventors:

Andy J. Liu - San Jose CA

Assignee:

Adaptec, Inc. - Milpitas CA

International Classification:

G06F 1300

US Classification:

395825

Abstract:

The transfer of multiple sectors of data between a hard disk drive and a computer data bus of a host computer is controlled by hardware within a computer bus interface circuit of a storage controller integrated circuit of this invention. Multiple sectors of data are transferred without intervention of a microprocessor that controls the operation of the disk drive containing the storage controller integrated circuit. The computer bus interface circuit of this invention not only automatically transfers data between the computer data bus and the computer bus interface circuit but also generates status information, generates interrupts to the host computer, and updates task file registers.