Anthony Nhat Le

US Patent:

6377065, Apr 23, 2002

Filed:

Apr 13, 2000

Appl. No.:

09/548875

Inventors:

Anthony Le - Santa Clara CA
Rochit Rajsuman - Santa Clara CA
James Alan Turnquist - Santa Clara CA
Shigeru Sugamori - Santa Clara CA

Assignee:

Advantest Corp. - Tokyo

International Classification:

G01R 3126

US Classification:

324765, 3241581, 714724

Abstract:

A semiconductor test system has a glitch detection function for detecting glitches in an output signal from a device under test to accurately evaluate the device under test (DUT). The semiconductor test system includes an event memory for storing event data, an event generator for producing test patterns, strobe signals and expected patterns based on the event data from the event memory, a pin electronics for transmitting the test pattern from the event generator to the DUT and receiving an output signal of the DUT and sampling the output signal by timings of the strobe signals, a pattern comparator for comparing sampled output data with the expected patterns, and a glitch detection unit for receiving the output signal from the DUT and detecting a glitch in the output signal by counting a number of edges in the output signal and comparing an expected number of edges.

US Patent:

6404218, Jun 11, 2002

Filed:

Apr 24, 2000

Appl. No.:

09/559365

Inventors:

Anthony Le - Santa Clara CA
James Alan Turnquist - Santa Clara CA
Rochit Rajsuman - Santa Clara CA
Shigeru Sugamori - Santa Clara CA

Assignee:

Advantest Corp. - Tokyo

International Classification:

G01R 3102

US Classification:

324763, 324765

Abstract:

An event based test system for testing semiconductor devices under test (DUT). The event based test system is freely configured to a plurality of groups of sin units where each group is able to perform test operations independently from the other. The start and end timings of the test in each group are independently made by generating multiple end of test signals. The event based test system includes a plurality of pin units to be assigned to pins of the DUT, a signal generator for generating an end of test signal for indicating an end of current test which is generated for each pin unit independently from other pin units, and a system controller for controlling an overall operation in the event based test system by communicating with each pin unit. The end of test signal for each pin unit is selected by condition specified by the system controller and the selected end of test signal is provided to the system controller and to the other pin units.

US Patent:

6578169, Jun 10, 2003

Filed:

Apr 8, 2000

Appl. No.:

09/545730

Inventors:

Anthony Le - Santa Clara CA
Rochit Rajsuman - Santa Clara CA
James Alan Turnquist - Santa Clara CA
Shigeru Sugamori - Santa Clara CA

Assignee:

Advantest Corp. - Tokyo

International Classification:

G01R 3128

US Classification:

714736, 714723

Abstract:

A semiconductor test system for testing a semiconductor device under test (DUT) is able to store failure data in a data failure memory with small memory capacity. The semiconductor test system includes a pattern memory for storing pattern data therein to produce a test pattern to be supplied to the DUT, means for evaluating an output signal of the DUT and producing failure data when there is a fail therein, a data failure memory for storing the failure data, and compaction means for assigning a plurality of addresses of the pattern memory to a single address of the data failure memory in a first test operation so that failure data occurred for each group of addresses of the pattern memory is stored in a corresponding address of the data failure memory, and for executing a second test operation for only a group of addresses of the pattern memory in which the failure data is detected without an address compaction.

US Patent:

6594609, Jul 15, 2003

Filed:

Nov 25, 2000

Appl. No.:

09/721828

Inventors:

Anthony Le - Santa Clara CA
Rochit Rajsuman - Santa Clara CA

Assignee:

Advantest, Corp. - Tokyo

International Classification:

G01R 3100

US Classification:

702117, 714731

Abstract:

An event based test system can generate scan vectors for testing a semiconductor device of scan design without requiring a large amount of scan memory. The test system includes an event memory for storing timing data and event type data of each event where the timing data is expressed by N data bits for defining one test vector, an event generator for generating an event with use of the timing data and the event type data, and a mode change circuit provided between the event memory and the event generator for changing signal paths between a normal mode for generating the test vectors and a scan mode for generating the scan vectors. In the test system, each bit of the N data bits in the event memory defines 2 scan vectors which are provided to the event generator in a series fashion, thereby producing the 2 scan vectors at each access of the event memory.

US Patent:

6622286, Sep 16, 2003

Filed:

Jun 30, 2000

Appl. No.:

09/608599

Inventors:

Tuan Ngo - Milpitas CA
Farro Kaveh - Palo Alto CA
Connie Lam - Los Altos CA
Chung-Ho Huang - Fremont CA
Tuqiang Ni - Fremont CA
Anthony T. Le - San Jose CA
Steven Salkow - Pleasanton CA

Assignee:

Lam Research Corporation - Fremont CA

International Classification:

G06F 1750

US Classification:

716 1, 716 19, 700121

Abstract:

A central controller for use in a semiconductor manufacturing equipment integrates a plurality of controllers with an open architecture allowing real-time communication between the various control loops. The central controller includes at least one central processing unit (CPU) executing high level input output (i/o) and control algorithms and at least one integrated i/o controller providing integrated interface to sensors and control hardware. The integrated i/o controller performs basic i/o and low level control functions and communicates with the CPU through a bus to perform or enable controls of various subsystems of the semiconductor manufacturing equipment.

US Patent:

6668331, Dec 23, 2003

Filed:

Mar 24, 2000

Appl. No.:

09/535031

Inventors:

Glen A. Gomes - Santa Clara CA
Anthony Le - Santa Clara CA
James Alan Turnquist - Santa Clara CA
Shigeru Sugamori - Santa Clara CA

Assignee:

Advantest Corp. - Tokyo

International Classification:

G06F 104

US Classification:

713401, 713400, 713500, 713502, 714715

Abstract:

An apparatus and method in an event based test system for testing an electronics device under test (DUT). The apparatus includes an event memory for storing timing data and event type data of each event wherein the timing data of a current event is expressed by a delay time from an event immediately prior thereto with use of a specified number of data bits, and an additional delay time inserted in the timing data of a specified event in such a way to establish a total delay time of the current event which is longer than that can be expressed by the specified number of data bits in the event memory. The additional delay time is inserted by replicating the timing data and the event type data of the event immediately prior to the specified event.

US Patent:

6710590, Mar 23, 2004

Filed:

Dec 12, 2002

Appl. No.:

10/319110

Inventors:

Niels Markert - Santa Clara CA
Anthony Le - Santa Clara CA
Hiroki Yamoto - Santa Clara CA
Robert Sauer - Santa Clara CA

Assignee:

Advantest Corporation - Ora-gun

International Classification:

G01R 3102

US Classification:

3241581, 324754

Abstract:

The present invention is directed to a test head Hifix of a semiconductor device testing apparatus that does not require disassembly for maintenance or repair of the semiconductor device testing apparatus. In one embodiment, the test head Hifix of a semiconductor device testing apparatus includes a plate that resides as the top surface of a test head and on which the assembly, loadboard, socket and DUT are mounted. The plate is attached to the test head in an arrangement that allows the plate along with the assembly, loadboard, socket and DUT to be easily moved without completely disassembling the plate, assembly and loadboard from the test head. In one embodiment, the plate is attached or coupled to the test head by hinges.

US Patent:

6747447, Jun 8, 2004

Filed:

Sep 25, 2002

Appl. No.:

10/254401

Inventors:

Niels Markert - Santa Clara CA
Anthony Le - Santa Clara CA
Robert Sauer - Santa Clara CA
Rochit Rajsuman - Santa Clara CA
Hiroki Yamoto - Santa Clara CA

Assignee:

Advantest Corporation - Ora-gun

International Classification:

G01R 3102

US Classification:

3241581, 324758, 324765

Abstract:

The present invention is directed to a locking apparatus and loadboard assembly of a semiconductor testing device apparatus. The loadboard assembly includes a printed circuit board containing a device under test and an interface board secured to the bottom of the printed circuit board. The interface board has two members with a space between them. Spacers connect the members to form apertures for contact pins on a test head. The loadboard assembly is placed on top of a locking apparatus which is mounted on the top surface of the test head. The placement of the loadboard on the locking apparatus is done according to two pins of different cross-sections that extend through two holes in the interface board and printed circuit board of the loadboard assembly. When the loadboard assembly is placed on the locking mechanism, rollers mounted on the interface board are received in cam slots of a cam member of the locking apparatus. These rollers follow the cam slots as the cam member is moved.