Aravind Natarajan

US Patent:

20180060130, Mar 1, 2018

Filed:

Aug 24, 2016

Appl. No.:

15/245604

Inventors:

- San Diego CA, US
Han Zhao - Santa Clara CA, US
Aravind Natarajan - Sunnyvale CA, US

International Classification:

G06F 9/50

Abstract:

Embodiments include computing devices, apparatus, and methods implemented by the apparatus for implementing speculative loop iteration partitioning (SLIP) for heterogeneous processing devices. A computing device may receive iteration information for a first partition of iterations of a repetitive process and select a SLIP heuristic based on available SLIP information and iteration information for the first partition. The computing device may determine a split value for the first partition using the SLIP heuristic, and partition the first partition using the split value to produce a plurality of next partitions.

US Patent:

20180052776, Feb 22, 2018

Filed:

Aug 18, 2016

Appl. No.:

15/239937

Inventors:

- San Diego CA, US
Arun Raman - San Francisco CA, US
Aravind Natarajan - Sunnyvale CA, US

International Classification:

G06F 12/109

Abstract:

Embodiments include computing devices, apparatus, and methods implemented by the apparatus for implementing shared virtual index translation on a computing device. The computing device may receive a base virtual address for storing an output of a kernel function execution to a dedicated memory and determine whether the virtual address is in a range of virtual addresses for a privatized output buffer within the dedicated memory, which may be smaller than the dedicated memory. The computing device may calculate a first modified physical address using a physical address mapped to the base virtual address and an offset of a first processing device associated with the dedicated memory in response to determining that the base virtual address is in the range of virtual addresses. The computing device may store the output of the kernel function execution to the privatized output buffer at the first modified physical address.

US Patent:

20170286182, Oct 5, 2017

Filed:

Mar 30, 2016

Appl. No.:

15/085108

Inventors:

- San Diego CA, US
Gheorghe Cascaval - Palo Alto CA, US
Han Zhao - Santa Clara CA, US
Tushar Kumar - San Jose CA, US
Aravind Natarajan - Sunnyvale CA, US
Arun Raman - Fremont CA, US

International Classification:

G06F 9/52

Abstract:

Embodiments include computing devices, systems, and methods identifying enhanced synchronization operation outcomes. A computing device may receive a first resource access request for a first resource of a computing device including a first requester identifier from a first computing element of the computing device. The computing device may also receive a second resource access request for the first resource including a second requester identifier from a second computing element of the computing device. The computing device may grant the first computing element access to the first resource based on the first resource access request, and return a response to the second computing element including the first requester identifier as a winner computing element identifier.

US Patent:

20170206035, Jul 20, 2017

Filed:

Jan 19, 2016

Appl. No.:

15/000667

Inventors:

- San Diego, CA
Aravind Natarajan - Sunnyvale CA, US
Dario Suarez Gracia - Teruel, ES

International Classification:

G06F 3/06
G06F 12/10

Abstract:

Methods, devices, and non-transitory processor-readable storage media for a computing device to merge concurrent writes from a plurality of processing units to a buffer associated with an application. An embodiment method executed by a processor may include identifying a plurality of concurrent requests to access the buffer that are sparse, disjoint, and write-only, configuring a write-set for each of the plurality of processing units, executing the plurality of concurrent requests to access the buffer using the write-sets, determining whether each of the plurality of concurrent requests to access the buffer is complete, obtaining a buffer index and data via the write-set of each of the plurality of processing units, and writing to the buffer using the received buffer index and data via the write-set of each of the plurality of processing units in response to determining that each of the plurality of concurrent requests to access the buffer is complete.

US Patent:

20170060633, Mar 2, 2017

Filed:

Aug 27, 2015

Appl. No.:

14/837156

Inventors:

- San Diego CA, US
Tushar Kumar - San Francisco CA, US
Aravind Natarajan - Sunnyvale CA, US
Ravish Hastantram - San Jose CA, US
Gheorghe Calin Cascaval - Palo Alto CA, US
Han Zhao - Santa Clara CA, US

International Classification:

G06F 9/50

Abstract:

Various embodiments include methods for data management in a computing device utilizing a plurality of processing units. Embodiment methods may include generating a data transfer heuristic model based on measurements from a plurality of sample data transfers between a plurality of data storage units. The generated data transfer heuristic model may be used to calculate data transfer costs for each of a plurality of tasks. The calculated data transfer costs may be used to schedule execution of the plurality of tasks in an execution order on selected ones of the plurality of processing units. The data transfer heuristic model may be updated based on measurements of data transfers occurring during the executions of the plurality of tasks (e.g., time, power consumption, etc.). Code executing on the processing units may indicate to a runtime when certain data blocks are no longer needed and thus may be evicted and/or pre-fetched for others.

US Patent:

20160292012, Oct 6, 2016

Filed:

Mar 30, 2015

Appl. No.:

14/673857

Inventors:

- San Diego CA, US
Shaizeen Dilawarhusen Aga - Ann Arbor MI, US
Dario Suarez Gracia - Santa Clara CA, US
Arun Raman - Santa Clara CA, US
Aravind Natarajan - Sunnyvale CA, US
Gheorghe Calin Cascaval - Palo Alto CA, US
Pablo Montesinos Ortego - Fremont CA, US
Han Zhao - Santa Clara CA, US

International Classification:

G06F 9/50

Abstract:

Embodiments include computing devices, systems, and methods for task-based handling of repetitive processes in parallel. At least one processor of the computing device, or a specialized hardware controller, may be configured to partition iterations of a repetitive process and assign the partitions to initialized tasks to be executed in parallel by a plurality of processor cores. Upon completing a task, remaining divisible partitions of the repetitive process of ongoing tasks may be subpartitioned and assigned to the ongoing task, and the completed task or a newly initialized task. Information about the iteration space for a repetitive process may be stored in a descriptor table, and status information for all partitions of a repetitive process stored in a status table. Each processor core may have an associated local table that tracks iteration execution of each task, and is synchronized with the status table.