Zeiss Group
Senior Manager
Tsmc
Quality and Reliability Department Manager
Tsmc
Senior Program Manager
Intel Corporation Oct 1995 - Jun 2016
Senior Staff Engineer
Intel Corporation Oct 1995 - Jun 2016
Senior Staff Enigeer
Education:
University of California, Berkeley 1986 - 1992
Doctorates, Doctor of Philosophy, Philosophy, Chemistry
University of California
Skills:
Semiconductors Design of Experiments Failure Analysis Thin Films R&D Characterization Electronics Physics Research and Development Optics Nanotechnology Semiconductor Industry Materials Science Microelectronics Simulations Engineering Management Microsoft Word Ic Integrated Circuits Semiconductor Process Technology Microelectronics Fault Isolation Semiconductor Process Microelectronics Design Debug Yield Management Cmos
Kyle Flanigan - Portland OR, US Baohua Niu - Portland OR, US Juan Dominguez - Hillsboro OR, US Ernisse Putna - Beaverton OR, US
International Classification:
G03C 5/00 G02F 1/13
US Classification:
430322000, 349002000, 430394000
Abstract:
A mask useful for photolithography that can be electronically reconfigured is described. In one embodiment, a photolithography system has an illumination system, a reticle scanning stage, a wafer scanning stage, and a reticle mounted to the reticle scanning stage, the reticle having an electronically reconfigurable mask.
Copper Bump Barrier Cap To Reduce Electrical Resistance
Ting Zhong - Tigard OR, US Shriram Ramanathan - Portland OR, US Gerald Leatherman - Hillsboro OR, US Baohua Niu - Portland OR, US Ebrahim Andideh - Portland OR, US
International Classification:
H01L 23/48 H01L 23/52 H01L 29/40
US Classification:
257734000
Abstract:
A controlled collapse chip connection (C4) comprises a copper metal C4 bump formed on an integrated circuit substrate, where the C4 bump includes a metal barrier cap to prevent electromigration of the copper metal. The barrier cap is formed from nickel or cobalt and it can either be formed on a top surface of the C4 bump or it can encapsulate the C4 bump. A method of forming the C4 bump with the barrier cap comprises providing an integrated circuit substrate, depositing a photoresist layer on a top surface of the integrated circuit substrate, exposing and developing the photoresist layer to form an opening, depositing copper metal into the opening to form a C4 bump, plating a metal barrier layer onto a surface of the C4 bump, and stripping the photoresist layer.
Baohua Niu - Portland OR, US Patrick M. Pardy - Hillsboro OR, US David L. Budka - Langhorne PA, US Mitchell L. Sacks - Aloha OR, US
International Classification:
H04N 5/225 F21V 9/14
US Classification:
348340, 362 19, 348E05024
Abstract:
Through silicon imaging and probing. A light source provides unpolarized light to be projected on a device under test (DUT). Light reflected from the DUT may be captured by a camera or other image capture device. A pellicle is utilized to reflect light from the light source toward the DUT. The pellicle also passes light reflected by the DUT to the camera. One or more linear polarizers or half wave plates may be used to provide the desired light polarization. The ability to provide the desired polarization provides an improved image that can be captured by the camera.
Generating Nano-Particles For Chemical Mechanical Planarization
An embodiment of the present invention is a technique to generate particles for use in a slurry solution for chemical mechanical planarization (CMP). Reverse micelles are formed using at least one of an oxide and a metal in a mixture. The size of the reverse micelles is tuned to a desired size. The particles are formed inside the reverse micelles. The particles are precipitated and transferred to a slurry solution.
Methods Of Cross-Section Imaging Of An Inspection Volume In A Wafer
- Oberkochen, DE Eugen Foca - Ellwangen, DE Chuong Huynh - Quincy MA, US Dmitry Klochkov - Schwaebisch Gmuend, DE Thomas Korb - Schwaebisch Gmuend, DE Jens Timo Neumann - Aalen, DE Baohua Niu - Livermore CA, US
The present disclosure relates to dual beam device and three-dimensional circuit pattern inspection techniques by cross sectioning of inspection volumes with large depth extension exceeding 1 μm below the surface of a semiconductor wafer, as well as methods, computer program products and apparatuses for generating 3D volume image data of a deep inspection volume inside a wafer without removal of a sample from the wafer. The disclosure further relates to 3D volume image generation and cross section image alignment methods utilizing a dual beam device for three-dimensional circuit pattern inspection.
A method of performing metrology analysis of a thin film includes coupling a radiation into an optical element disposed adjacent to a surface of the thin film. The radiation is coupled such that the radiation is totally internally reflected at an interface between the optical element and the thin film. An evanescent radiation generated at the interface penetrates the thin film. The method furthers include analyzing the evanescent radiation scattered by the thin film to obtain properties of the thin film.
Method For Writing To Magnetic Random Access Memory
- Hsinchu, TW Jhong-Sheng WANG - Taichung City, TW Baohua NIU - Portland OR, US
International Classification:
G11C 11/16
Abstract:
A method of manufacturing an array of magnetic random access memory cells includes writing to a magnetic random access memory cell. The writing to a memory cell includes determining an optimum write current for the array of memory cells, and applying the optimum write current to a first memory cell in the array. A first read current is applied to the first memory cell to determine whether a magnetic orientation of the first memory cell has changed in response to applying the optimum write current. A second write current is applied to the first memory cell when the magnetic orientation of the first memory cell has not changed. The second write current is different from the optimum write current. A second read current is applied to the first memory cell to determine whether the magnetic orientation of the first memory cell changed in response to applying the second write current.
Magnetic Detection Circuit, Mram And Operation Method Thereof
A magnetic detection circuit for a magnetic random access memory (MRAM) is provided. The magnetic detection circuit includes a sensing array and a controller. The sensing array includes a plurality of sensing cells, and each of plurality of sensing cells includes a first magnetic tunnel junction (MTJ) device. The controller is configured to periodically write and read the sensing cells to obtain a difference between first data written to the sensing cells and second data read from the sensing cells. When the difference between the first data and the second data is greater than a threshold value, the controller is configured to stop a write operation of a plurality of memory cells of the MRAM until the difference between the first data and the second data is less than the threshold value.