Barry J Flahive

Address:

2 Parker Cir, Westford, MA 01886

Phone:

9786923248

VIN:

WBANV93518CW55424

Make:

BMW

Model:

5 SERIES

Year:

2008

US Patent:

6286095, Sep 4, 2001

Filed:

Sep 26, 1995

Appl. No.:

8/533878

Inventors:

Dale C. Morris - Menlo Park CA
Barry J. Flahive - Westford MA
Michael L. Ziegler - Whitinsville MA
Jerome C. Huck - Palo Alto CA
Stephen G. Burger - Santa Clara CA
Ruby B. L. Lee - Los Altos CA
Bernard L. Stumpf - Chelmsford MA
Jeff Kurtze - Nashua NH

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1314

US Classification:

712216

Abstract:

A computer apparatus incorporating special instructions to force load and store operations to execute in program order. The present invention provides a new and novel store instruction that is suspended until all prior store instructions have been completed by an associated CPU. Also, a new load instruction is provided which blocks any subsequent load instructions from executing until this load instruction has been completed by an associated CPU. These instructions allow for high efficiency computer systems to be implemented which optimize instruction throughput by executing subsequent instructions while waiting for a prior instruction to complete.

US Patent:

51670224, Nov 24, 1992

Filed:

Jul 16, 1990

Appl. No.:

7/552341

Inventors:

Richard G. Bahr - Cambridge MA
Andrew Milia - Burlington MA
Barry J. Flahive - Westford MA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1336
G06F 13368

US Classification:

395325

Abstract:

A method and apparatus for granting, to a select processor in a multiprocessor computing system, exclusive access to a bus for issuance of address, data and command signals thereover, wherein each processor includes bus lock request and bus lock assert elements which provide corresponding bus request and bus hold signals which are recognized by corresponding elements included in other processors connected to the bus. The bus lock according to the present invention assures the processor having lock status of privacy on the bus necessary to complete a specified operation without interruption from the other processors.

US Patent:

44491832, May 15, 1984

Filed:

Oct 13, 1981

Appl. No.:

6/310825

Inventors:

Barry J. Flahive - Westford MA
John J. Grady - Woburn MA
Peter J. Rado - Acton MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

G06F 1300

US Classification:

364200

Abstract:

An arbitration network for use in a data multiprocessing system that includes a functional unit, such as a memory module, that is shared by several requestor devices, such as data processors, wherein access is granted to the shared functional unit through a common data bus on a rotating priority basis and wherein the arbitration cycle of the functional unit for determining priorities of the requestor devices is performed near the end of each operational cycle of the functional unit so that the next requestor device initiates its operational cycle immediately succeeding a current operational cycle then transacting thereby to minimize idle bus periods which would otherwise occur during arbitration cycle sequencing. When the bus is idle and only one request for access is made, the arbitration network foregoes the complete arbitration cycle and issues the grant to the requesting device thereby providing an earlier initiation of the data transfer cycle of the functional unit.

US Patent:

42901332, Sep 15, 1981

Filed:

Oct 25, 1978

Appl. No.:

5/954604

Inventors:

Robert E. Stewart - Stow MA
Barry J. Flahive - Westford MA
David Potter - Pepperell MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

H04J 308

US Classification:

370 85

Abstract:

A digital data processing system including an interconnection for the various elements that constitute the system. Each element that connects to the interconnection is called a nexus, and each nexus in the system can communicate with other nexuses. A central clocking circuit generates timing signals that control such communications on a synchronous basis. The clocking circuit includes oscillator, control and sequencing circuits that produce phase and clocking signals that are coupled to each nexus. Each nexus contains receivers and decoders for converting the phase and clocking signals into a sequence of internal timing signals that synchronizes the operation of the nexus to transfers among the nexuses.

US Patent:

47559365, Jul 5, 1988

Filed:

Jan 29, 1986

Appl. No.:

6/823805

Inventors:

Robert E. Stewart - Stow MA
Barry J. Flahive - Westford MA
James B. Keller - Arlington MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

G06F 1300

US Classification:

364200

Abstract:

A cache memory unit is disclosed in which, in response to the application of a write command, the write operation is performed in two system clock cycles. During the first clock cycle, the data signal group is stored in a temporary storage unit while a determination is made if the address signal group associated with the data signal group is present in the cache memory unit. When the address signal group is present, the data signal group is stored in the cache memory unit during the next application of a write command to the cache memory unit. If a read command is applied to the cache memory unit involving the data signal group stored in the temporary storage unit, then this data signal group is transferred to the central processing unit in response to the read command. Instead of performing the storage into the cache memory unit as a result of the next write command, the storage of the data signal in the cache memory unit can occur during any free cycle.

US Patent:

51758296, Dec 29, 1992

Filed:

Oct 25, 1988

Appl. No.:

7/262495

Inventors:

Bernard Stumpf - Chelmsford MA
George M. Stabler - Nashua NH
Richard G. Bahr - Cambridge MA
Stephen J. Ciavaglia - Nashua NH
Barry J. Flahive - Westford MA
Hugh Lauer - Concord MA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 900
G06F 1300

US Classification:

395375

Abstract:

A computer system having a plurality of processors sharing common memory and data bus structures and operable to perform atomic operations which comprise several instruction actions, wherein the processor performing the atomic operation prevents memory access interruptions by other processors by locking out other processors during the atomic operation. The system bus includes signal paths accommodating bus lock request and bus lock signals which are provided and received by each processor, which signals are initiated by specific bus lock and lock release instructions added to each processor instruction set.

US Patent:

60790121, Jun 20, 2000

Filed:

Nov 6, 1997

Appl. No.:

8/968923

Inventors:

Dale C. Morris - Menlo Park CA
Bernard L. Stumpf - Chelmsford MA
Barry J. Flahive - Westford MA
Jeffrey D. Kurtze - Nashua NH
Stephen G. Burger - Santa Clara CA
Ruby B. L. Lee - Los Altos CA
William R. Bryg - Saratoga CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 15163

US Classification:

712216

Abstract:

A computer apparatus which detects a store or load operation into or from a shared memory page by a program that does not provide for synchronization when executed by a CPU that completes instructions out of program order. After the store or load is detected, the CPU explicitly orders operations into the shared memory page. Store operations are ordered such that no new store into the shared memory page is performed until all prior store operations into the shared memory page are complete. Also, load operations are ordered such that load operations from the shared memory page are performed in program order. This ordering is achieved by maintaining a process bit and a memory attribute bit associated with a shared memory page. When both bits are true, all load or store operations referencing the shared memory page are ordered.

US Patent:

48602442, Aug 22, 1989

Filed:

Nov 7, 1983

Appl. No.:

6/549608

Inventors:

William F. Bruckert - Hudson MA
Barry Flahive - Westford MA
James V. Lacy - Northboro MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

G06F 900

US Classification:

364900

Abstract:

A data transfer system for use in transferring data between a memory and an input/output system in a digital data processing system. The data transfer system includes a plurality of buffers into which data can be loaded from the memory or the input/output system. A buffer control selects the buffer to be loaded, and control signals from the memory govern the transfer of data from the memory into and out of the selected buffer.