Benjamin L Louie

US Patent:

7120068, Oct 10, 2006

Filed:

Jul 29, 2002

Appl. No.:

10/206044

Inventors:

Vinod Lakhani - Palo Alto CA, US
Benjamin Louie - Fremont CA, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 7/00

US Classification:

365200, 36523006, 36523003, 36518905, 36523008

Abstract:

A scheme for defective memory column or row substitution is disclosed which uses a programmable look-up table to store new addresses for column selection when certain column or row addresses are received. The new addresses are loaded into a programmable fuse latch each time an address transition is detected in the input address.

US Patent:

7123512, Oct 17, 2006

Filed:

Jul 19, 2002

Appl. No.:

10/199725

Inventors:

Vinod Lakhani - Palo Alto CA, US
Benjamin Louie - Fremont CA, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 11/00

US Classification:

36518509, 365200, 36523001, 711103

Abstract:

An improved non-volatile erase block memory device apparatus and method is described that incorporates an improved addressing scheme to provide for extended addressing allowing redundant erase blocks that are not utilized to repair general use erase blocks of the main memory array to be accessed and utilized as additional storage space by an end user. The additional storage space formed by the unused redundant erase blocks and the specified storage space of the main memory array is presented to the end user as a single contiguous address space. Additionally, the redundant erase blocks can be utilized to repair any damaged erase block in the memory array of the non-volatile erase block memory or Flash memory device regardless of bank placement.

US Patent:

7123521, Oct 17, 2006

Filed:

Apr 27, 2005

Appl. No.:

11/115489

Inventors:

Benjamin Louie - Fremont CA, US
Yunqiu Wan - Mountain View CA, US
Aaron Yip - Santa Clara CA, US
Jin-Man Han - Santa Clara CA, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 7/10

US Classification:

36518905, 36523003

Abstract:

A non-volatile memory is described that utilizes a cache read mode of operation, where a next page of memory is being read/sensed from the memory array by the sense amplifiers while a previously read page of memory is being read from the memory I/O buffer, wherein the next page is user selected. This random cache read mode allows for a memory with a random page read capability, in which the address of the next page of data to be read is user selectable, which benefits from the low latency of a cache read mode of operation due to concurrent data sensing and data I/O.

US Patent:

7154780, Dec 26, 2006

Filed:

Aug 18, 2005

Appl. No.:

11/206529

Inventors:

Vinod Lakhani - Palo Alto CA, US
Benjamin Louie - Fremont CA, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 11/00

US Classification:

36518509, 365200, 36523001, 711103

Abstract:

An improved non-volatile erase block memory device apparatus and method is described that incorporates an improved addressing scheme to provide for extended addressing allowing redundant erase blocks that are not utilized to repair general use erase blocks of the main memory array to be accessed and utilized as additional storage space by an end user. The additional storage space formed by the unused redundant erase blocks and the specified storage space of the main memory array is presented to the end user as a single contiguous address space. Additionally, the redundant erase blocks can be utilized to repair any damaged erase block in the memory array of the non-volatile erase block memory or Flash memory device regardless of bank placement.

US Patent:

7154781, Dec 26, 2006

Filed:

Aug 18, 2005

Appl. No.:

11/207017

Inventors:

Vinod Lakhani - Palo Alto CA, US
Benjamin Louie - Fremont CA, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 11/00

US Classification:

36518509, 365200, 36523001, 711103

Abstract:

An improved non-volatile erase block memory device apparatus and method is described that incorporates an improved addressing scheme to provide for extended addressing allowing redundant erase blocks that are not utilized to repair general use erase blocks of the main memory array to be accessed and utilized as additional storage space by an end user. The additional storage space formed by the unused redundant erase blocks and the specified storage space of the main memory array is presented to the end user as a single contiguous address space. Additionally, the redundant erase blocks can be utilized to repair any damaged erase block in the memory array of the non-volatile erase block memory or Flash memory device regardless of bank placement.

US Patent:

7154782, Dec 26, 2006

Filed:

Aug 18, 2005

Appl. No.:

11/207105

Inventors:

Vinod Lakhani - Palo Alto CA, US
Benjamin Louie - Fremont CA, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 11/00

US Classification:

36518509, 365200, 36523001, 711103

Abstract:

An improved non-volatile erase block memory device apparatus and method is described that incorporates an improved addressing scheme to provide for extended addressing allowing redundant erase blocks that are not utilized to repair general use erase blocks of the main memory array to be accessed and utilized as additional storage space by an end user. The additional storage space formed by the unused redundant erase blocks and the specified storage space of the main memory array is presented to the end user as a single contiguous address space. Additionally, the redundant erase blocks can be utilized to repair any damaged erase block in the memory array of the non-volatile erase block memory or Flash memory device regardless of bank placement.

US Patent:

7159141, Jan 2, 2007

Filed:

Jul 1, 2002

Appl. No.:

10/184961

Inventors:

Vinod Lakhani - Palo Alto CA, US
Benjamin Louie - Fremont CA, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 11/00

US Classification:

714 8, 714710

Abstract:

A scheme for block substitution within a flash memory device is disclosed which uses a programmable look-up table to store new addresses for block selection when certain input block addresses are received. The new addresses are loaded into a programmable fuse latch each time an address transition is detected in the input address. The new addresses may contain block addresses or block and bank addresses.

US Patent:

7213188, May 1, 2007

Filed:

Aug 31, 2004

Appl. No.:

10/930153

Inventors:

Benjamin Louie - Fremont CA, US
Judy Wan - Mountain View CA, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G01R 31/28

US Classification:

714742, 714724

Abstract:

An integrated circuit device receives a sequence of commands and enables a test mode of the integrated circuit device in response to the command sequence when all of the commands of the sequence are correct. The integrated circuit device disables the test mode upon receiving an incorrect command of the sequence.