Benjamin J Louie

US Patent:

6370070, Apr 9, 2002

Filed:

Jun 21, 2001

Appl. No.:

09/886543

Inventors:

Christophe J. Chevallier - Mountain View CA
Benjamin Louie - Sunnyvale CA

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 700

US Classification:

365201, 36518509

Abstract:

Memory devices having architectures permitting the application of a voltage differential across alternate bitlines facilitate identifying and locating shorts within the memory device with particular reference to flash memory devices. The memory devices include a first plurality of selective coupling devices coupled between a first plurality of bitlines and a first variable potential node. The memory devices further include a second plurality of selective coupling devices coupled between a second plurality of bitlines and a second variable potential node. The first plurality of selective coupling devices are responsive to a first control signal to selectively provide electrical communication between the first plurality of bitlines and the first variable potential node. The second plurality of selective coupling devices are responsive to a second control signal to selectively provide electrical communication between the second plurality of bitlines and the second variable potential node. Each variable potential node provides two or more potential states.

US Patent:

7120068, Oct 10, 2006

Filed:

Jul 29, 2002

Appl. No.:

10/206044

Inventors:

Vinod Lakhani - Palo Alto CA, US
Benjamin Louie - Fremont CA, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 7/00

US Classification:

365200, 36523006, 36523003, 36518905, 36523008

Abstract:

A scheme for defective memory column or row substitution is disclosed which uses a programmable look-up table to store new addresses for column selection when certain column or row addresses are received. The new addresses are loaded into a programmable fuse latch each time an address transition is detected in the input address.

US Patent:

7123512, Oct 17, 2006

Filed:

Jul 19, 2002

Appl. No.:

10/199725

Inventors:

Vinod Lakhani - Palo Alto CA, US
Benjamin Louie - Fremont CA, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 11/00

US Classification:

36518509, 365200, 36523001, 711103

Abstract:

An improved non-volatile erase block memory device apparatus and method is described that incorporates an improved addressing scheme to provide for extended addressing allowing redundant erase blocks that are not utilized to repair general use erase blocks of the main memory array to be accessed and utilized as additional storage space by an end user. The additional storage space formed by the unused redundant erase blocks and the specified storage space of the main memory array is presented to the end user as a single contiguous address space. Additionally, the redundant erase blocks can be utilized to repair any damaged erase block in the memory array of the non-volatile erase block memory or Flash memory device regardless of bank placement.

US Patent:

7123521, Oct 17, 2006

Filed:

Apr 27, 2005

Appl. No.:

11/115489

Inventors:

Benjamin Louie - Fremont CA, US
Yunqiu Wan - Mountain View CA, US
Aaron Yip - Santa Clara CA, US
Jin-Man Han - Santa Clara CA, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 7/10

US Classification:

36518905, 36523003

Abstract:

A non-volatile memory is described that utilizes a cache read mode of operation, where a next page of memory is being read/sensed from the memory array by the sense amplifiers while a previously read page of memory is being read from the memory I/O buffer, wherein the next page is user selected. This random cache read mode allows for a memory with a random page read capability, in which the address of the next page of data to be read is user selectable, which benefits from the low latency of a cache read mode of operation due to concurrent data sensing and data I/O.

US Patent:

7154780, Dec 26, 2006

Filed:

Aug 18, 2005

Appl. No.:

11/206529

Inventors:

Vinod Lakhani - Palo Alto CA, US
Benjamin Louie - Fremont CA, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 11/00

US Classification:

36518509, 365200, 36523001, 711103

Abstract:

An improved non-volatile erase block memory device apparatus and method is described that incorporates an improved addressing scheme to provide for extended addressing allowing redundant erase blocks that are not utilized to repair general use erase blocks of the main memory array to be accessed and utilized as additional storage space by an end user. The additional storage space formed by the unused redundant erase blocks and the specified storage space of the main memory array is presented to the end user as a single contiguous address space. Additionally, the redundant erase blocks can be utilized to repair any damaged erase block in the memory array of the non-volatile erase block memory or Flash memory device regardless of bank placement.

US Patent:

7154781, Dec 26, 2006

Filed:

Aug 18, 2005

Appl. No.:

11/207017

Inventors:

Vinod Lakhani - Palo Alto CA, US
Benjamin Louie - Fremont CA, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 11/00

US Classification:

36518509, 365200, 36523001, 711103

Abstract:

An improved non-volatile erase block memory device apparatus and method is described that incorporates an improved addressing scheme to provide for extended addressing allowing redundant erase blocks that are not utilized to repair general use erase blocks of the main memory array to be accessed and utilized as additional storage space by an end user. The additional storage space formed by the unused redundant erase blocks and the specified storage space of the main memory array is presented to the end user as a single contiguous address space. Additionally, the redundant erase blocks can be utilized to repair any damaged erase block in the memory array of the non-volatile erase block memory or Flash memory device regardless of bank placement.

US Patent:

7154782, Dec 26, 2006

Filed:

Aug 18, 2005

Appl. No.:

11/207105

Inventors:

Vinod Lakhani - Palo Alto CA, US
Benjamin Louie - Fremont CA, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 11/00

US Classification:

36518509, 365200, 36523001, 711103

Abstract:

An improved non-volatile erase block memory device apparatus and method is described that incorporates an improved addressing scheme to provide for extended addressing allowing redundant erase blocks that are not utilized to repair general use erase blocks of the main memory array to be accessed and utilized as additional storage space by an end user. The additional storage space formed by the unused redundant erase blocks and the specified storage space of the main memory array is presented to the end user as a single contiguous address space. Additionally, the redundant erase blocks can be utilized to repair any damaged erase block in the memory array of the non-volatile erase block memory or Flash memory device regardless of bank placement.

US Patent:

7159141, Jan 2, 2007

Filed:

Jul 1, 2002

Appl. No.:

10/184961

Inventors:

Vinod Lakhani - Palo Alto CA, US
Benjamin Louie - Fremont CA, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 11/00

US Classification:

714 8, 714710

Abstract:

A scheme for block substitution within a flash memory device is disclosed which uses a programmable look-up table to store new addresses for block selection when certain input block addresses are received. The new addresses are loaded into a programmable fuse latch each time an address transition is detected in the input address. The new addresses may contain block addresses or block and bank addresses.