Bin B Liu

US Patent:

6414557, Jul 2, 2002

Filed:

Feb 17, 2000

Appl. No.:

09/507114

Inventors:

Bin Liu - Danville CA

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03B 502

US Classification:

331 57, 327261, 327266, 327272, 327274

Abstract:

A ring oscillator circuit, such as a VCO, with a relatively high level of noise rejection for noise originating from both the voltage supply and ground. The ring oscillator circuit is composed of a plurality of differential delay circuits, each differential delay circuit generating a differential output signal that is a delayed (and preferably inverted) version of a differential input signal. Each differential delay circuit includes first and second input transistors for receiving the differential input signal. Each differential delay circuit also includes first and second load transistors coupled in parallel with the respective first and second input transistors. Each differential delay circuit further includes a first current source coupled between the first input transistor and a first power supply terminal (e. g. , a voltage supply terminal), a second current source coupled between the second input transistor and the first power supply terminal and a third current source coupled between the first and second input transistors and a second power supply terminal (e. g. , a ground terminal).

US Patent:

6426407, Jul 30, 2002

Filed:

Jun 7, 1995

Appl. No.:

08/473888

Inventors:

Jacques R. Fresco - Princeton NJ
Bin Liu - San Francisco CA
Lynn C. Klotz - Somerville MA

Assignee:

Codon Pharm. - Gaithersburg MD
Princeton Univ. - Princeton NJ

International Classification:

C07H 2102

US Classification:

536 221, 536 231, 536 243, 536 2431, 536 2433, 514 49, 435 5, 435 6, 435 912

Abstract:

The invention relates to compositions of matter capable of serving as residues for specific binding of third strands to double-stranded complementary nucleic acids of any base-pair sequence.

US Patent:

6560449, May 6, 2003

Filed:

Jun 12, 2000

Appl. No.:

09/591925

Inventors:

Bin Liu - Danville CA

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H04B 110

US Classification:

455302, 455205

Abstract:

In a communications receiver for quadrature demodulation, a feedback technique for reducing the image response of the receiver. The communications receiver includes an I demodulator and a Q demodulator. A local oscillator (LO) signal is provided by a PLL to a quadrature LO generator that provides an LO_I signal to an I demodulator and an LO_Q signal to a Q demodulator. The LO_I and LO_Q signals are amplitude and phase-controlled versions of the LO signal. An image/signal ratio (I/S) detector detects the relative phase difference and the relative amplitude difference between the respective output terminals of the I demodulator and the Q demodulator and applies an amplitude control signal and a phase control signal to corresponding amplitude control and phase control inputs of the quadrature LO generator. The I/S detector calibrates the quadrature LO generator during the interstitial interval between the reception of data packets. The control signals from the I/S detector adjust the relative amplitude and phase of the LO_I and LO_Q signals in a manner that reduces the image response of the communications receiver.

US Patent:

6657503, Dec 2, 2003

Filed:

Apr 25, 2002

Appl. No.:

10/131963

Inventors:

Bin Liu - Danville CA

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03B 2700

US Classification:

331 57, 331183, 331185, 327261, 327266, 327272, 327274

Abstract:

A ring oscillator circuit, such as a VCO, with a relatively high level of noise rejection for noise originating from both the voltage supply and ground. The ring oscillator circuit is composed of a plurality of differential delay circuits, each differential delay circuit generating a differential output signal that is a delayed (and preferably inverted) version of a differential input signal. Each differential delay circuit includes first and second input transistors for receiving the differential input signal. Each differential delay circuit also includes first and second load transistors coupled in parallel with the respective first and second input transistors. Each differential delay circuit further includes a first current source coupled between the first input transistor and a first power supply terminal (e. g. , a voltage supply terminal), a second current source coupled between the second input transistor and the first power supply terminal and a third current source coupled between the first and second input transistors and a second power supply terminal (e. g. , a ground terminal).

US Patent:

6778594, Aug 17, 2004

Filed:

Jun 12, 2000

Appl. No.:

09/592016

Inventors:

Bin Liu - Danville CA

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H04B 138

US Classification:

375222, 455302

Abstract:

A communications receiver architecture characterized by a relatively low intermediate frequency (IF) and a polyphase filter. The receiver includes an input amplifier coupled to a carrier signal. Respective I and Q demodulators are coupled to the output of the input amplifier. A quadrature local oscillator (LO) generator provides respective LO_I and LO_Q inputs to the I demodulator and LO_Q inputs to the I demodulator and to the Q demodulator. The quadrature LO generator is driven by a phase-locked LO, and the LO frequency is such that an IF of, in one embodiment, approximately 1 MHz results. The I demodulator and Q demodulator outputs are applied through respective A/D converters to a polyphase filter. The polyphase filter outputs are then processed by a digital I/Q demodulator. Although a low IF is not generally understood to promote the image rejection performance of a receiver, substantial image rejection is afforded by the polyphase filter, thereby enabling the receiver to be realized almost entirely as a monolithic integrated semiconductor device.

US Patent:

6828866, Dec 7, 2004

Filed:

Oct 6, 2003

Appl. No.:

10/679839

Inventors:

Bin Liu - Danville CA

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03B 532

US Classification:

331 57, 331185, 331183, 327274

Abstract:

A ring oscillator circuit, such as a VCO, with a relatively high level of noise rejection for noise originating from both the voltage supply and ground. The ring oscillator circuit is composed of a plurality of differential delay circuits, each differential delay circuit generating a differential output signal that is a delayed (and preferably inverted) version of a differential input signal. âEach differential delay circuit includes first and second input transistors for receiving the differential input signal. Each differential delay circuit also includes first and second load transistors coupled in parallel with the respective first and second input transistors. Each differential delay circuit further includes a first current source coupled between the first input transistor and a first power supply terminal (e. g. , a voltage supply terminal), a second current source coupled between the second input transistor and the first power supply terminal and a third current source coupled between the first and second input transistors and a second power supply terminal (e. g. , a ground terminal).

US Patent:

6963251, Nov 8, 2005

Filed:

Nov 18, 2004

Appl. No.:

10/992426

Inventors:

Bin Liu - Danville CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03B005/02

US Classification:

331 57, 327261, 327266, 327272, 327274

Abstract:

A ring oscillator circuit, such as a VCO, with a relatively high level of noise rejection for noise originating from both the voltage supply and ground. The ring oscillator circuit is composed of a plurality of differential delay circuits, each differential delay circuit generating a differential output signal that is a delayed (and preferably inverted) version of a differential input signal. ‘Each differential delay circuit includes first and second input transistors for receiving the differential input signal. Each differential delay circuit also includes first and second load transistors coupled in parallel with the respective first and second input transistors. Each differential delay circuit further includes a first current source coupled between the first input transistor and a first power supply terminal (e. g. , a voltage supply terminal), a second current source coupled between the second input transistor and the first power supply terminal and a third current source coupled between the first and second input transistors and a second power supply terminal (e. g. , a ground terminal).

US Patent:

6981197, Dec 27, 2005

Filed:

Jan 23, 2002

Appl. No.:

10/057831

Inventors:

Bin Liu - Newark CA, US
Edmun ChianSong Seng - Singapore, SG
UttHeng Kan - Singapore, SG

Assignee:

Seagate Technology LLC - Scotts Valley CA

International Classification:

G11C029/00

US Classification:

714765

Abstract:

An enhanced interleave type error correction method is provided in which decoding of an enhanced interleave block is done. Subsequently the decoding may be done by decoding the estimated codewords multiple times using a single error correction code. In addition, a decoder and a digital communication system for implementing the enhanced interleave type error correction method are provided.