Binh Phuoc Ngo

US Patent:

6891426, May 10, 2005

Filed:

Oct 19, 2001

Appl. No.:

10/056657

Inventors:

Raymond Zeng - Folsom CA, US
Binh N. Ngo - Folsom CA, US

Assignee:

Intel Corporation - Hillsboro OR

International Classification:

G05F001/10

US Classification:

327536, 327534, 327540, 327415, 327416

Abstract:

A method of providing multiple voltage outputs includes receiving an input signal from a multifunctional pump. The method also includes sending a first output signal based on the input signal using a first switch and sending a second output signal based on the input signal using a second switch and a transistor.

US Patent:

60727233, Jun 6, 2000

Filed:

May 6, 1999

Appl. No.:

9/306322

Inventors:

Sandeep K. Guliani - Folsom CA
Binh N. Ngo - Folsom CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 1600

US Classification:

36518518

Abstract:

A bias circuit for a memory cell having first and second floating gate devices, and third and fourth reference devices, one of which has an output terminal coupled thereto is described. In one embodiment, the bias circuit includes a first capacitor including a first terminal coupled to the gates of the first and second devices, and a second terminal coupled to a power supply terminal, and a second capacitor including a first terminal coupled to the gates of the third and fourth devices, and a second terminal coupled to the power supply terminal. The bias circuit further includes a reference circuit including a first terminal having a first signal thereon and coupled to the gates of the first and second devices, and a second terminal having a second signal thereon and coupled to the gates of the third and fourth devices, the reference circuit to periodically turn on the first and second signals. The bias circuit reduces standby current and wake up time of redundant circuits in non-volatile memory devices.

US Patent:

20220415380, Dec 29, 2022

Filed:

Jun 24, 2021

Appl. No.:

17/357466

Inventors:

- Santa Clara CA, US
Aliasgar S. Madraswala - Folsom CA, US
Bharat Pathak - Folsom CA, US
Binh Ngo - Folsom CA, US
Netra Mahuli - Folsom CA, US
Ahsanur Rahman - Santa Clara CA, US

International Classification:

G11C 11/4076
G11C 11/408
G11C 11/4094
G11C 11/4096

Abstract:

Systems, apparatuses and methods may provide for technology that sends a first command to a NAND die, sends first address information to the NAND die, and sends a second command to the NAND die, wherein the first command and the second command define a first command sequence and wherein the first address information signal a beginning of a first asynchronous read request from a first plurality of planes. In one example, the technology also sends a second command sequence and second address information to the NAND die wherein the second command sequence signals an end of the first asynchronous read request.

US Patent:

20230079077, Mar 16, 2023

Filed:

Oct 17, 2022

Appl. No.:

18/047097

Inventors:

- Santa Clara CA, US
Binh Ngo - Folsom CA, US

International Classification:

G11C 8/08
G11C 8/10
G11C 8/16

Abstract:

Technology herein provides a performance-enhanced memory device including a memory array including a local word line circuit and a plurality of local word lines coupled to the local word line circuit, a word line (WL) sense circuit coupled to an access node in the local word line circuit, the WL sense circuit to sense a voltage level in the local word line circuit while bypassing a disturbance to operation of the local word lines and to provide an output signal that indicates when the voltage level has reached a high voltage threshold value to enable a read operation. The technology also provides read logic coupled to the WL sense circuit, the read logic to receive the output signal from the WL sense circuit, and trigger a read operation for one or more cells in the memory array when the output signal indicates that the voltage level has reached the high voltage threshold value.

US Patent:

20230082368, Mar 16, 2023

Filed:

Sep 15, 2021

Appl. No.:

17/475880

Inventors:

- Santa Clara CA, US
Binh Ngo - Folsom CA, US
Ahsanur Rahman - Folsom CA, US
Radhika Chinnammagari - Folsom CA, US
Sagar Upadhyay - Folsom CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 16/08
G11C 16/04

Abstract:

Systems, apparatuses, and methods may provide for technology that groups a plurality of wordline drivers together and supports these grouped wordline drivers via a shared multiplexer, a shared level shifter, and/or one or more shared multi-well level shifters. In one example, such technology includes a shared multiplexer and a first and second grouped global wordline driver coupled to the shared multiplexer. The shared multiplexer is to access data state information from a plurality of memory cells. The first grouped global wordline driver is to output a first plurality of wordlines associated with a first plane. The second grouped global wordline driver is to output a second plurality of wordlines associated with a second plane, where the second plane is different than the first plane.

US Patent:

20200090743, Mar 19, 2020

Filed:

Oct 4, 2019

Appl. No.:

16/593868

Inventors:

- Santa Clara CA, US
Bharat M. PATHAK - Folsom CA, US
Binh N. NGO - Folsom CA, US
Naveen VITTAL PRABHU - Folsom CA, US
Karthikeyan RAMAMURTHI - Folsom CA, US
Pranav KALAVADE - San Jose CA, US

International Classification:

G11C 11/56
G11C 8/08
G11C 16/26
G11C 16/08

Abstract:

A system for facilitating multiple concurrent page reads in a memory array is provided. Memory cells that have multiple programming states (e.g., store multiple bits per cell) rely on various control gate and wordline voltages levels to read the memory cells. Therefore, to concurrently read multiple pages of memory cells, where each page includes one or more different programming levels, a memory controller includes first wordline control logic that includes a first voltage regulator and includes second wordline control logic that includes a second voltage regulator, according to one embodiment. The two voltage regulators enable the memory controller to concurrently address and access multiple pages of memory at different programming levels, in response to memory read requests, according to one embodiment.

US Patent:

20190043564, Feb 7, 2019

Filed:

Dec 18, 2017

Appl. No.:

15/845500

Inventors:

- Santa Clara CA, US
BHARAT M. PATHAK - Folsom CA, US
BINH N. NGO - Folsom CA, US
NAVEEN VITTAL PRABHU - Folsom CA, US
KARTHIKEYAN RAMAMURTHI - Folsom CA, US
PRANAV KALAVADE - San Jose CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 11/56
G11C 16/08
G11C 16/26

Abstract:

A system for facilitating multiple concurrent page reads in a memory array is provided. Memory cells that have multiple programming states (e.g., store multiple bits per cell) rely on various control gate and wordline voltages levels to read the memory cells. Therefore, to concurrently read multiple pages of memory cells, where each page includes one or more different programming levels, a memory controller includes first wordline control logic that includes a first voltage regulator and includes second wordline control logic that includes a second voltage regulator, according to one embodiment. The two voltage regulators enable the memory controller to concurrently address and access multiple pages of memory at different programming levels, in response to memory read requests, according to one embodiment.