Brian W Erickson

US Patent:

6363019, Mar 26, 2002

Filed:

Nov 3, 2000

Appl. No.:

09/706242

Inventors:

Brian D. Erickson - Soquel CA
Barry Wong - Los Gatos CA
Patrick T. Bever - Santa Clara CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G11C 700

US Classification:

36518907, 36518901, 36523008

Abstract:

A programmable logic device (PLD) including a non-volatile memory array for persistently storing configuration data, and a volatile memory array for temporarily storing the configuration data and controlling the various logic resources of the PLD to perform a users logic operation. When the PLD is reset, an addressing circuit causes a column of non-volatile memory cells to transmit configuration data values to a corresponding column of volatile memory cells on a series of write lines. To verify that a configuration data value is successfully written from each non-volatile memory cell to a corresponding volatile memory cell, the data value transmitted on each write line is compared with the stored data value transmitted from each volatile memory cell on a corresponding read line. A control signal is generated when all of the data values transmitted on the write lines are equal to stored data values transmitted on corresponding read lines, thereby indicating that the configuration data values are successfully transferred to the column of volatile memory cells. The control signal is used to increment the address circuit, thereby addressing a next sequential column of non-volatile memory cells and associated volatile memory cells.

US Patent:

6529041, Mar 4, 2003

Filed:

Mar 23, 2001

Appl. No.:

09/816799

Inventors:

Mark M. Ng - San Jose CA
Brian D. Erickson - Soquel CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 19177

US Classification:

326 40, 326 38, 326 39, 326 41, 326 83

Abstract:

A power control output circuit for a PLD that allows the PLD to selectively operate in either a low current (ânormalâ) output mode, or a high current power control mode. In one embodiment, the power control output circuit is incorporated into a special Input/Output Blocks (PC-IOB) of the PLD. When no power control function is needed, a high current output portion of the power control output circuit is deactivated by storing an associated data value a power control configuration memory cell of the PLD, and an output driver of the PC-IOB generates low current output signals on a device I/O terminal. To perform power control functions, a portion of the PLDs programmable logic circuitry is configured to generate a power control data signal, and the high current output portion of the power control output circuit is enabled by storing a corresponding data value in the power control configuration memory cell. When the power control data signal is generated while in the high current power control mode, the high current output circuit turns on a high current transistor that generates a high current power control output signal at the device I/O terminal.

US Patent:

6873842, Mar 29, 2005

Filed:

Mar 30, 2001

Appl. No.:

09/823591

Inventors:

Bernardo Elayda - San Jose CA, US
Brian D. Erickson - Soquel CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H04B007/00

US Classification:

455418, 455419, 455420

Abstract:

A wireless programmable logic device contains a wireless component and a programmable logic component. A remote wireless host can be used to program the programmable logic device. Some product designs require multiple programmable logic devices. When wireless programmable logic devices are used in the design, all of them can receive data and commands from the host. As a result, the wireless host can control the order of configuration and the start time of these logic devices. There is no need to build glue logic for this purpose. Consequently, the efficiency in product design is improved. If there are problems in programming a programmable logic device, the host can log the failed operation in its memory. This information could be used to improve production flow.

US Patent:

7302562, Nov 27, 2007

Filed:

Nov 5, 2004

Appl. No.:

10/981931

Inventors:

Neil G. Jacobson - Los Altos CA, US
Sanjay Srivastava - San Jose CA, US
Bin Dai - Mountain View CA, US
Sungnien Mao - Fremont CA, US
Pushpasheel Tawade - San Jose CA, US
David E. Schweigler - Campbell CA, US
Brian D. Erickson - Soquel CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 7/38

US Classification:

713100, 326 37, 326 38, 716 16

Abstract:

Method and system for a programmable device programmer. The disclosure describes various embodiments for programming a target programmable device by a programmer. In one embodiment, the programmer determines availability of updated configuration data for a hardware component of the programmer. The programmer includes the software component coupled to the hardware component. An update mode of the hardware component is enabled in response to availability of the updated configuration data, and programming of the target programmable device is disabled while the hardware component is in the update mode. A programmable device internal to the hardware component is programmed with the updated configuration data while the hardware component is in the update mode, and the update mode is disabled in response to completion of programming of the at least one programmable device. A target programmable device may then be programmed by the programmer having the updated configuration data.

US Patent:

7480491, Jan 20, 2009

Filed:

Feb 8, 2005

Appl. No.:

11/053479

Inventors:

Brian D. Erickson - Soquel CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H04B 1/38

US Classification:

455 903, 455 901, 455418, 375219

Abstract:

A wireless programmable logic device contains a wireless component and a programmable logic component. A remote wireless host can be used to program the programmable logic device. Some product designs require multiple programmable logic devices. When wireless programmable logic devices are used in the design, all of them can receive data and commands from the host. As a result, the wireless host can control the order of configuration and the start time of these logic devices. There is no need to build glue logic for this purpose. Consequently, the efficiency in product design is improved. If there are problems in programming a programmable logic device, the host can log the failed operation in its memory. This information could be used to improve production flow.

US Patent:

20110282836, Nov 17, 2011

Filed:

May 17, 2010

Appl. No.:

12/781535

Inventors:

Brian Erickson - Long Beach CA, US
Yevgeny Naryzhny - Foothill Ranch CA, US
Vinay Kamath - Rancho Santa Margarita CA, US
Clement Lie - Mission Viejo CA, US
Elliott Middleton - Tyler TX, US

Assignee:

Invensys Systems, Inc. - Foxboro MA

International Classification:

G06F 17/30

US Classification:

707622, 707E17005

Abstract:

A multi-tiered replicated process database and corresponding method are disclosed for supporting replication between tiers. The multi-tiered replicated process database comprises a tier one (T1) database server computer including a process history database and a replication service. The replication service includes a set of accumulators. Each accumulator is adapted to render a summary T2 database tag data structure from a set of data values retrieved from the process history database for a specified T1 database tag. The replicated database system also includes a tier two (T2) database server computer comprising a consolidated database that includes process data replicated from a set of T1 database servers. At least a portion of the process data replicated from the set of T1 database servers is summary T2 database tag data rendered by the set of accumulators.

US Patent:

20110282866, Nov 17, 2011

Filed:

May 17, 2010

Appl. No.:

12/781662

Inventors:

Brian Erickson - Long Beach CA, US
Vinay Kamath - Rancho Santa Margarita CA, US
Elliott Middleton - Tyler TX, US

Assignee:

Invensys Systems, Inc. - Foxboro MA

International Classification:

G06F 17/30

US Classification:

707722, 707E17044

Abstract:

A database server for handling steams of time stamped data points for tagged variables is disclosed herein that supports a set of advanced data retrieval operations/queries invoked by clients of the database server. The advanced data retrieval operations are invoked by client queries to provide, on demand, secondary information by processing previously tabled data corresponding to received data streams rendered by a variety of data sources in a supervisory control/monitoring, process control and/or automated equipment environment. Calculations, on previously stored data, for rendering the secondary information are performed within the database server at the time the secondary information is requested by a client of the historian that maintains a database containing the previously stored data. Moreover, a filtering stage and enhanced time-in-state processing operations are supported.

US Patent:

20130096643, Apr 18, 2013

Filed:

Dec 4, 2012

Appl. No.:

13/705021

Inventors:

Nevro Corporation - Menlo Park CA, US
Anthony V. Caparso - San Jose CA, US
Brian J. Erickson - Woodbury MN, US
Konstantinos Alataris - Belmont CA, US
Andre B. Walker - Monte Sereno CA, US

Assignee:

Nevro Corporation - Menlo Park CA

International Classification:

A61N 1/36

US Classification:

607 46

Abstract:

Multi-frequency neural treatments and associated systems and methods are disclosed. A method in accordance with a particular embodiment includes at least reducing patient pain by applying a first electrical signal to a first target location of the patient's spinal cord region at a frequency in a first frequency range of up to about 1,500 Hz, and applying a second electrical signal to a second target location of the patient's spinal cord region at a frequency in a second frequency range of from about 2,500 Hz to about 100,000 Hz.