Brian Matthew Zimmerman

US Patent:

62861263, Sep 4, 2001

Filed:

Apr 13, 1999

Appl. No.:

9/292783

Inventors:

Vivek Raghavan - Mountain View CA
Brian A. Zimmerman - San Jose CA

Assignee:

Avant! Corporation - Fremont CA

International Classification:

G06F 1750

US Classification:

716 6

Abstract:

Methods, apparatus and computer program products are provided that perform the operations of extracting first estimates of the resistance and capacitance of each of a first plurality of nets in an integrated circuit and then determining, for each of the first plurality of nets, a respective maximum delay model that attributes all of the first estimate of the resistance of the respective net to a front-end of the net and all of the first estimate of the capacitance of the respective net to a back-end of the net. Respective minimum delay models are also obtained for each of the first plurality of nets. Each of these minimum delay models attributes all of the first estimate of the resistance of the respective net to the back-end of the net and all of the first estimate of the capacitance of the respective net to a front-end of the net. These minimum and maximum delay models are then used in the determination of minimum and maximum delay estimates for each of the first plurality of nets. The delay estimates are then used to determine a net timing error bound associated with each net.