Brian A Zimmerman

US Patent:

8043270, Oct 25, 2011

Filed:

Nov 3, 2005

Appl. No.:

11/718541

Inventors:

Matthew D Burke - Research Triangle Park NC, US
Chinmay R Maheshwari - Research Triangle Park NC, US
Brian O Zimmerman - Research Triangle Park NC, US

Assignee:

GlaxoSmith Kline LLC - Philadelphia PA

International Classification:

A61M 37/00

US Classification:

60428801

Abstract:

An apparatus and method are provided for analyzing the release of active agent(s) from pharmaceutical and pharmaceutical-like products. The apparatus and method provide for more accurate simulation of the conditions in the GI tract including forces that are applied to the dosage form.

US Patent:

58963006, Apr 20, 1999

Filed:

Aug 30, 1996

Appl. No.:

8/706182

Inventors:

Vivek Raghavan - Durham NC
Brian Allan Zimmerman - Durham NC

Assignee:

Avant| Corporation - Freemont CA

International Classification:

G06F 1700
G06F 1750

US Classification:

364491

Abstract:

A method, apparatus and computer program product performs a bounded parasitic extraction of typically all nets in an integrated circuit as part of a series of post-layout verification operations. According to one embodiment, a resistance-only extraction and/or a capacitance-only extraction is initially performed using computationally inexpensive electrical models of the nets. The resistance and capacitance extractions may be combined with models of the active devices to generate realistic worst case and best case delay models for each of the extracted nets. The delay models may be based on the resistance-only extraction and an upper bound on the parasitic capacitance of the net determined from the capacitance-only extraction, however, other models based solely on a resistance-only extraction may also be used, although they are typically less preferred. A user-specified timing error tolerance is then used to automatically determine the appropriate level of additional extraction detail to be applied to the specific nets in the integrated circuit. This gives the user direct error control over the extraction process so that the extracted netlist meets the user-specified timing error tolerance in an efficient manner.

US Patent:

62861263, Sep 4, 2001

Filed:

Apr 13, 1999

Appl. No.:

9/292783

Inventors:

Vivek Raghavan - Mountain View CA
Brian A. Zimmerman - San Jose CA

Assignee:

Avant! Corporation - Fremont CA

International Classification:

G06F 1750

US Classification:

716 6

Abstract:

Methods, apparatus and computer program products are provided that perform the operations of extracting first estimates of the resistance and capacitance of each of a first plurality of nets in an integrated circuit and then determining, for each of the first plurality of nets, a respective maximum delay model that attributes all of the first estimate of the resistance of the respective net to a front-end of the net and all of the first estimate of the capacitance of the respective net to a back-end of the net. Respective minimum delay models are also obtained for each of the first plurality of nets. Each of these minimum delay models attributes all of the first estimate of the resistance of the respective net to the back-end of the net and all of the first estimate of the capacitance of the respective net to a front-end of the net. These minimum and maximum delay models are then used in the determination of minimum and maximum delay estimates for each of the first plurality of nets. The delay estimates are then used to determine a net timing error bound associated with each net.