Charles W Graham

US Patent:

60852771, Jul 4, 2000

Filed:

Oct 15, 1997

Appl. No.:

8/950755

Inventors:

Gregory Michael Nordstrom - Oronoco MN
Shawn Michael Lambeth - Pine Island MN
Paul Edward Movall - Rochester MN
Daniel Frank Moertl - Rochester MN
Charles Scott Graham - Rochester MN
William Joseph Armstrong - Kasson MN
Thomas Rembert Sand - Rochester MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1300

US Classification:

710263

Abstract:

An interrupt and message batching apparatus and method reduces the number and frequency of processor interrupts and resulting context switches by grouping I/O completion events together with a single processor interrupt in a manner that balances I/O operation latency requirements with processor utilization requirements to optimize overall computer system performance. The invention sends a message from a processor complex to an I/O adapter on an I/O bus commanding an I/O device connected to the I/O adapter to perform a function. Upon completion of the commanded function, the message processor in the I/O adapter generates a message and sends it to the processor complex on the I/O bus. The message is enqueued in the message queue of the memory, a message count is updated, and processor complex interrupt is signalled if and when the message count exceeds a message pacing count. A signalling timer may also be programmed with a fast response time value if the message has a relatively high latency or with a slow response time value if the message has a relatively low latency.

US Patent:

59832924, Nov 9, 1999

Filed:

Oct 15, 1997

Appl. No.:

8/950593

Inventors:

Gregory Michael Nordstrom - Oronoco MN
Shawn Michael Lambeth - Pine Island MN
Paul Edward Movall - Rochester MN
Daniel Frank Moertl - Rochester MN
Charles Scott Graham - Rochester MN
Thomas Rembert Sand - Rochester MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1310
G06F 1314

US Classification:

710 54

Abstract:

An I/O system including a processor complex and system main memory connected to I/O adapters via I/O adapters and I/O bus. A message transport mechanism and method stores an upstream message queue and a downstream message queue in system main memory. Queue addresses are stored both in system main memory and designated registers of I/O adapters. The I/O adapters utilize the queue addresses to manage the transfer of downstream command messages and to send upstream response messages to the system main memory via direct memory access across the I/O bus.

US Patent:

60732539, Jun 6, 2000

Filed:

Dec 19, 1997

Appl. No.:

8/995075

Inventors:

Gregory Michael Nordstrom - Oronoco MN
Shawn Michael Lambeth - Pine Island MN
Paul Edward Movall - Rochester MN
Daniel Frank Moertl - Rochester MN
Charles Scott Graham - Rochester MN
Paul John Johnsen - Rochester MN
Thomas Rembert Sand - Rochester MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1100

US Classification:

714 25

Abstract:

An apparatus, system and method permitting a variety of reset procedures and corresponding reset states. A device reset control register is provided for each I/O device adapter in single function or multifunction devices. The device reset control registers permit a greater degree of control over single function devices, multifunction device as a whole and individual device functions within a multifunction device. A device immediate status register synchronizes the various reset procedures. A logical power on reset procedure, a directed unit reset procedure and a directed interface reset procedure utilize the greater degree of control that the device reset control registers provide to force the I/O device adapter, single function device or multifunction device into a corresponding logical power on reset state, a directed unit reset state or a directed interface reset state. Each of these reset states is well-defined and has the advantage of predictable behavior during and after execution of the corresponding reset procedure. A built-in self-test procedure is also defined that sequentially examines each function associated within a multifunction device connected to the local bus to coordinate the initiation, execution and completion of built in self-tests.