Christopher Edward Koob

US Patent:

6668313, Dec 23, 2003

Filed:

Dec 21, 2001

Appl. No.:

10/026350

Inventors:

Christopher Koob - Pflugerville TX
David P. Sonnier - Austin TX

Assignee:

Agere Systems, Inc. - Allentown PA

International Classification:

G06F 1206

US Classification:

711170

Abstract:

A system and method for memory management in a high-speed network environment. Multiple packets are interleaved in data streams and sent to a Memory Manager System. Read and write requests are queued in FIFO buffers. Subsets of these requests are grouped and ordered to optimize processing. This method employs a special arbitration scheme between read and write accesses. Read and write requests are treated as atomic. Memory bank selection is optimized for the request being processed. Alternating between memory bank sets is done to minimize bank conflicts. Link list updates are pipelined. Multiple independent link lists may be supported with the inclusion of a link list identifier. Arbitration between read and write requests continues until the group is exhausted. Then, processing is repeated for the next requests in the BRAM (buffer memories).

US Patent:

6801991, Oct 5, 2004

Filed:

Dec 21, 2001

Appl. No.:

10/037163

Inventors:

Hanan Z. Moller - Austin TX
David P. Sonnier - Austin TX
Christopher Koob - Pflugerville TX

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

G06F 1202

US Classification:

711173

Abstract:

An apparatus and method for moving and/or resizing logical buffers that comprise a memory space without the loss of data. Each buffer comprises a linear and contiguous set of storage locations, and operates according to a FIFO priority scheme, using a read address pointer to indicate the location from which data is read from the buffer and a write address pointer indicating the address into which data is written. A buffer is relocated or resized within the memory space by changing the base location address (defining the lowest storage location comprising the buffer) and/or the top location address (defining the highest memory location within the buffer) into free storage locations. To accomplish this relocation or resizing without the loss of data, the read address is first checked to determine if it bears an appropriate relationship to the new base and top memory locations.

US Patent:

7111289, Sep 19, 2006

Filed:

Dec 21, 2001

Appl. No.:

10/026351

Inventors:

Christopher Koob - Pflugerville TX, US
David P. Sonnier - Austin TX, US

Assignee:

Agere Systems, Inc. - Allentown PA

International Classification:

G06F 9/44

US Classification:

717152, 717162, 711170, 711171, 711172, 711173

Abstract:

A method is disclosed for free memory allocation in a linked list memory scheme. Free lists are link lists designating available memory for data storage. This method leverages the ability to read memory while concurrently updating a pointer to the next location. Multiple free lists are used to reduce the number of cycles necessary to allocate memory. The number of entries in each free list is tracked. When memory becomes available, it is spliced into the shortest free list to achieve balance between the free lists. The free list structure disclosed consists of head, head +1, and tail pointers where head +1 is the next logical address pointed to from the head pointer location. The free list consists only of the head and tail pointers. Each link list structure of memory to be freed contains the head, head +1, and tail pointers. This allows us to simultaneously allocate and free with only 1 memory cycle.

US Patent:

7313089, Dec 25, 2007

Filed:

Dec 21, 2001

Appl. No.:

10/037165

Inventors:

Hanan Z. Moller - Austin TX, US
David P. Sonnier - Austin TX, US
Christopher Koob - Pflugerville TX, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

G01R 31/08

US Classification:

370219, 370220

Abstract:

A switching system for a data traffic network. A plurality of line cards provide input and output connections to a plurality of data lines and further are connected to at least two switch fabrics, one of which is designated the active switch fabric and the other designated the standby switch fabric. Data traffic is switched between the plurality of input and output line cards by the active switch fabric. When it is desired to change the active switch fabric assignment, for example due to a fault in the switch fabric, data transmissions into the active switch fabric are terminated and a drain timer is started. When the drain timer times out or the active switch provides an indication that it is empty, the active switch fabric assignment is swapped to the standby switch fabric and data is then switched through the newly assigned active switch fabric.

US Patent:

7584233, Sep 1, 2009

Filed:

Jun 28, 2005

Appl. No.:

11/170288

Inventors:

Christopher Edward Koob - Round Rock TX, US
Jian Liang - San Diego CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

G06F 7/00

US Classification:

708211

Abstract:

A system and method is disclosed and includes an execution unit that can be used to count the leading zeros in a data word. During operation, the execution unit can receive a data word that has a width of 2 to the Nth power. Further, the execution unit can sign extend the data word to a temporary data word that has a width of 2 to the Mth power, wherein M is greater than N. The temporary data word can be input to a counter that has a width of 2 to the Mth power and the counter can count the leading zeros within the temporary data word to get a result.

US Patent:

7797366, Sep 14, 2010

Filed:

Feb 15, 2006

Appl. No.:

11/356359

Inventors:

Shankar Krithivasan - Austin TX, US
Christopher Edward Koob - Round Rock TX, US
William C. Anderson - Austin TX, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

G06F 7/52

US Classification:

708628, 708629

Abstract:

Techniques for the design and use of a digital signal processor, including processing transmissions in a communications (e. g. , code division multiple access) system. Power-efficient sign extension for Booth multiplication processes involves applying a sign bit in a Booth multiplication tree. The sign bit allows the Booth multiplication process to perform a sign extension step. This further involves one-extending a predetermined partial product row of the Booth multiplication tree using a sign bit for preserving the correct sign of the predetermined partial product row. The process and system resolve the signal value of the sign bit by generating a sign-extension bit in the Booth multiplication tree. The sign-extension bit is positioned in a carry-out column to extend the product of the Booth multiplication process. Then, the method and system form a final product from the Booth multiplication tree by adding the carry-out value to the sign bit positioned at least a predetermined column of the Booth multiplication tree.

US Patent:

7801164, Sep 21, 2010

Filed:

Apr 27, 2006

Appl. No.:

11/412917

Inventors:

Christopher Koob - Round Rock TX, US
Ali A. Poursepanj - Austin TX, US
David P. Sonnier - Austin TX, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H04L 12/56

US Classification:

370412

Abstract:

Improved timeout table mechanism are disclosed. By way of example, a method for providing timeout delays for data queues in a processing system includes the following steps. A timeout structure is maintained. The timeout structure includes two or more groups, each group including two or more bins, each bin having a range of timeout delay values associated therewith, each group having a weight associated therewith, the weight of each group being based on a rate and a quantity of queues assignable to each group. A timeout delay value to be assigned to a data queue in the processing system is selected.

US Patent:

7809783, Oct 5, 2010

Filed:

Feb 15, 2006

Appl. No.:

11/355397

Inventors:

Shankar Krithivasan - Austin TX, US
Christopher Edward Koob - Round Rock TX, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

G06F 7/52

US Classification:

708628

Abstract:

Techniques for the design and use of a digital signal processor, including processing transmissions in a communications (e. g. , CDMA) system. A modified Booth multiplication system and process determine a multiplicand, A, and a multiplier, B. Radix-m, (e. g. , radix-4) Booth recoding on B generates “n” multiplication factors, where “n,” an integer, is approximating one half of the number of the multiplier bits. “n” partial products are generated using the “n” multiplication factors as multipliers of A. Then, a multiplication tree is formed using radix-m Booth encoding. The multiplication tree includes multiplier bits associated to generate a multiplication factors. In the event of a negative multiplication factor, a two's complement of A is formed by inverting the bits of A and associating a sticky “1” to complete the two's complementation. Furthermore, multiplication factors are reduced in multiple stages to a form sum and carry components of a pre-determined length. The additive inverse of A×B is formed by using novel techniques to calculate the product of A and −B.