Clement K Leung

US Patent:

D504727, May 3, 2005

Filed:

Jul 9, 2003

Appl. No.:

29/186110

Inventors:

Tamara Lynn Schirrmacher - Alameda CA, US
Clement Gar-Kwok Leung - San Ramon CA, US
David Selby Maltz - San Francisco CA, US

Assignee:

Coolsystems, Inc. - Berkeley CA

International Classification:

2404

US Classification:

D24206, D24190

US Patent:

7356454, Apr 8, 2008

Filed:

Oct 18, 2004

Appl. No.:

10/967814

Inventors:

Hirofumi Sakane - Newark DE, US
Levent Yakay - Elkton MD, US
Vishal Karna - Newark DE, US
Clement Leung - Reston VA, US
Guang R. Gao - Newark DE, US

Assignee:

UD Technology Corporation - Newark DE

International Classification:

G06F 9/455

US Classification:

703 23, 703 28, 703 25, 703 16, 716 4, 716 16, 714710

Abstract:

A method for emulating a logic circuit having at least one set of identical logic modules is disclosed. Each logic module in a set has logic elements and memory elements that store a module state of that logic module. The logic circuit is emulated by extracting a logic module from a set of identical logic modules, translating the extracted logic module for iterative representation of the module state of each of the logic modules with a single instance of the logic elements, and configuring a logic device with the translated logic module to emulate the logic circuit.

US Patent:

7849441, Dec 7, 2010

Filed:

Jun 27, 2006

Appl. No.:

11/426882

Inventors:

Shridhar Mukund - San Jose CA, US
Anjan Mitra - Santa Clara CA, US
Jed Krohnfeldt - Los Gatos CA, US
Clement Leung - Fremont CA, US

Assignee:

iKoa Corporation - Menlo Park CA

International Classification:

G06F 9/44

US Classification:

717108

Abstract:

A method for specifying stateful, transaction-oriented systems is provided. The method initiates with designating a plurality of primitive FlowModules. The method includes defining at least one FlowGate within each of the plurality of FlowModules, wherein each FlowGate includes a non-interruptible sequence of procedure code, a single point of entry and is invoked by a named concurrent call. An Arc is designated from a calling FlowGate to a called FlowGate and a Signal is generated for each named invocation of the called FlowGate. A Channel is defined for carrying the Signal. Methods for synthesizing a semiconductor device and routing signals in the semiconductor device are provided.

US Patent:

20110035722, Feb 10, 2011

Filed:

Oct 18, 2010

Appl. No.:

12/906967

Inventors:

Shridhar Mukund - San Jose CA, US
Anjan Mitra - Santa Clara CA, US
Jed Krohnfeldt - Los Gatos CA, US
Clement Leung - Fremont CA, US

International Classification:

G06F 9/44

US Classification:

717104

Abstract:

A method for specifying stateful, transaction-oriented systems is provided. The method initiates with designating a plurality of primitive FlowModules. The method includes defining at least one FlowGate within each of the plurality of FlowModules, wherein each FlowGate includes a non-interruptible sequence of procedure code, a single point of entry and is invoked by a named concurrent call. An Arc is designated from a calling FlowGate to a called FlowGate and a Signal is generated for each named invocation of the called FlowGate. A Channel is defined for carrying the Signal. Methods for synthesizing a semiconductor device and routing signals in the semiconductor device are provided.

US Patent:

59008873, May 4, 1999

Filed:

May 5, 1997

Appl. No.:

8/850467

Inventors:

Clement K. Leung - Fremont CA
Ravi Ranganathan - Cupertino CA

Assignee:

NeoMagic Corp. - Santa Clara CA

International Classification:

G06F 1316

US Classification:

345521

Abstract:

A graphics controller chip has an integrated graphics memory. A wide data interface is provided to a RAM array storing graphics pixel data in the graphics memory. The wide data interface provides 256 bits of data during normal writes, but in a block-write mode the wide data interface is split into two sections. One section contains 128 bits of data, while a second section contains 128 mask bits. The data is replicated to eight half-width columns in the RAM array, while the mask bits disable writing some of the data to the RAM. Separate byte-mask bits can be provided for disabling bytes during normal mode writes, but these byte-mask bits cause multiple copies of the data to be disabled. Thus the mask bits in the second section are more useful as they can disable any individual byte in any of the eight columns. A block write of 64 2-byte pixels can be performed in a single step, as no color-data register and no mask register is needed.