Colyn S Case

US Patent:

6820173, Nov 16, 2004

Filed:

Feb 23, 2001

Appl. No.:

09/791417

Inventors:

Donald A. Bittel - San Jose CA
Colyn S. Case - Grass Valley CA

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06F 1200

US Classification:

711137, 711213

Abstract:

A system, method and article of manufacture are provided for retrieving information from memory. Initially, processor requests for information from a first memory are monitored. A future processor request for information is then predicted based on the previous step. Thereafter, one or more speculative requests are issued for retrieving information from the first memory in accordance with the prediction. The retrieved information is subsequently cached in a second memory for being retrieved in response to processor requests without accessing the first memory. By allowing multiple speculative requests to be issued, throughput of information in memory is maximized.

US Patent:

7278008, Oct 2, 2007

Filed:

Jan 30, 2004

Appl. No.:

10/769357

Inventors:

Colyn S. Case - Grass Valley CA, US
Dmitry Vyshetsky - Cupertino CA, US
Sean J. Treichler - Mountain View CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06F 12/00

US Classification:

711209, 711206, 710 26

Abstract:

A virtual address translation table and an on-chip address cache are usable for translating virtual addresses to physical addresses. Address translation information is provided using a cluster that is associated with some range of virtual addresses and that can be used to translate any virtual address in its range to a physical address, where the sizes of the ranges mapped by different clusters may be different. Clusters are stored in an address translation table that is indexed by virtual address so that, starting from any valid virtual address, the appropriate cluster for translating that address can be retrieved from the translation table. Recently retrieved clusters are stored in an on-chip cache, and a cached cluster can be used to translate any virtual address in its range without accessing the address translation table again.

US Patent:

7296139, Nov 13, 2007

Filed:

Jan 30, 2004

Appl. No.:

10/769326

Inventors:

Colyn S. Case - Grass Valley CA, US
Dmitry Vyshetsky - Cupertino CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06F 12/10

US Classification:

711209, 711206, 710 26

Abstract:

A virtual address translation table and an on-chip address cache are usable for translating virtual addresses to physical addresses. Address translation information is provided using a cluster that is associated with some range of virtual addresses and that can be used to translate any virtual address in its range to a physical address, where the sizes of the ranges mapped by different clusters may be different. Clusters are stored in an address translation table that is indexed by virtual address so that, starting from any valid virtual address, the appropriate cluster for translating that address can be retrieved from the translation table. Recently retrieved clusters are stored in an on-chip cache, and a cached cluster can be used to translate any virtual address in its range without accessing the address translation table again.

US Patent:

7334108, Feb 19, 2008

Filed:

Jan 30, 2004

Appl. No.:

10/769388

Inventors:

Colyn S. Case - Grass Valley CA, US
Dmitry Vyshetsky - Cupertino CA, US
Sean J. Treichler - Mountain View CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06F 12/10

US Classification:

711209, 711206, 710 26

Abstract:

A virtual address translation table and an on-chip address cache are usable for translating virtual addresses to physical addresses. Address translation information is provided using a cluster that is associated with some range of virtual addresses and that can be used to translate any virtual address in its range to a physical address, where the sizes of the ranges mapped by different clusters may be different. Clusters are stored in an address translation table that is indexed by virtual address so that, starting from any valid virtual address, the appropriate cluster for translating that address can be retrieved from the translation table. Recently retrieved clusters are stored in an on-chip cache, and a cached cluster can be used to translate any virtual address in its range without accessing the address translation table again.

US Patent:

7386697, Jun 10, 2008

Filed:

Mar 10, 2005

Appl. No.:

11/077662

Inventors:

Colyn S. Case - Hyde Park VT, US
Gary D. Lorensen - San Jose CA, US
Sharon Rose Clay - Los Altos CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06F 12/08

US Classification:

711171, 711209, 710 9

Abstract:

In a virtual memory system, address translation information is provided using a cluster that is associated with some range of virtual addresses and that can be used to translate any virtual address in its range to a physical address, where the sizes of the ranges mapped by different clusters may be different. Clusters are stored in an address translation table that is indexed by virtual address so that, starting from any valid virtual address, the appropriate cluster for translating that address can be retrieved from the translation table. The clusters are dynamically created from a fragmented pool of physical addresses as new virtual address mappings are requested by consumers of the virtual memory space.

US Patent:

7415575, Aug 19, 2008

Filed:

Dec 8, 2005

Appl. No.:

11/298256

Inventors:

Peter C. Tong - Cupertino CA, US
Colyn S. Case - Hyde Park VT, US

Assignee:

NVIDIA, Corporation - Santa Clara CA

International Classification:

G06F 12/12

US Classification:

711133, 711159, 711129

Abstract:

A cache shared by multiple clients implements a client specific policy for replacing entries in the event of a cache miss. A request from any client can hit any entry in the cache. For purposes of replacing entries, at least of the clients is restricted, and when a cache miss results from a request by the restricted client, the entry to be replaced is selected from a fixed subset of the cache entries. When a cache misses results from a request by any client other than the restricted client, any cache entry, including a restricted entry, can be selected to be replaced.

US Patent:

7469311, Dec 23, 2008

Filed:

Dec 19, 2006

Appl. No.:

11/613150

Inventors:

William P. Tsu - San Jose CA, US
Colyn S. Case - Hyde Park VT, US

Assignee:

Nvidia Corporation - Santa Clara CA

International Classification:

G06F 13/40

US Classification:

710307, 710 29

Abstract:

A bus interface permits an upstream bandwidth and a downstream bandwidth to be separately selected. In one implementation a link control module forms a bidirectional link with another bus interface by separately configuring link widths of an upstream unidirectional sub-link and a downstream unidirectional sub-link.

US Patent:

7526593, Apr 28, 2009

Filed:

Oct 3, 2006

Appl. No.:

11/538399

Inventors:

Manas Mandal - Palo Alto CA, US
William P. Tsu - San Jose CA, US
Colyn S. Case - Hyde Park VT, US
Ashish Kishen Kaul - Santa Clara CA, US

Assignee:

Nvidia Corporation - Santa Clara CA

International Classification:

G06F 13/36
G06F 13/00

US Classification:

710310, 710 35, 370473, 370474, 370393, 370465

Abstract:

Multiple data transfer requests can be merged and transmitted as a single packet on a packetized bus such as a PCI Express (PCI-E) bus. In one embodiment, requests are combined if they are directed to contiguous address ranges in the same target device. An opportunistic merging procedure is advantageously used that merges a first request with a later request if the first request and the later request are mergeable and are received within a holdoff period that is dynamically determined based on a level of bus activity; otherwise, requests can be transmitted without merging.