Dale Edward Wilson

US Patent:

6954083, Oct 11, 2005

Filed:

Dec 29, 2003

Appl. No.:

10/750232

Inventors:

Randal Thornley - Nampa ID, US
Gyle D. Yearsley - Boise ID, US
Dale Wilson - Nampa ID, US
Joshua J. Nekl - Nampa ID, US
William J. Tiffany - Boise ID, US

Assignee:

ZiLOG, Inc. - San Jose CA

International Classification:

H03K019/00

US Classification:

326 16, 326 9, 326 14

Abstract:

Fast electromagnetic transient (EFT) events of short duration are often not detected by power-on reset circuitry of an integrated circuit (IC). A fault detector circuit involves many fault detectors. The fault detectors are distributed across the IC and may be embodied in spare cells left in a standard cell IC. Each fault detector is initialized with a digital logic value. The fault detector circuit is then controlled such that the digital logic value stored should not change if the IC is operated under normal operating conditions. An EFT event that is undetected by the power-on reset circuit may, however, cause one of the digital logic values stored in one of the fault detectors to switch. If the digital logic value stored in any one of the fault detectors switches, then a fault signal is provided to the power-on reset circuit that in turn resets the IC.

US Patent:

7898009, Mar 1, 2011

Filed:

Feb 22, 2007

Appl. No.:

11/678026

Inventors:

Dale G. Wilson - Kuna ID, US
Kelly James DeGregorio - Boise ID, US
Stephen A. Parke - Cookeville TN, US

Assignee:

American Semiconductor, Inc. - Boise ID

International Classification:

H01L 29/80

US Classification:

257278

Abstract:

Memory cells are constructed from double-gated four terminal transistors having independent gate control. DRAM cells may use one, two or three transistors. Single transistor cells are constructed either with or without a bit storage capacitor, and both NAND- and NOR-type Non-Volatile NVRAM cells, as well as Ferroelectric FeRAM cells, are described. For all cells, top gates provide conventional access while independent bottom gates provide control to optimize memory retention for given speed and power parameters as well as to accommodate hardening against radiation. In a single transistor cell without a capacitor, use of the bottom gate allows packing to a density approaching 2 F. Using a ferroelectric material as the gate insulator produces a single-transistor FeRAM cell that overcomes the industry-wide Write Disturb problem. The memory cells are compatible with SOI logic circuitry for use as embedded RAM in SOC applications.

US Patent:

8089108, Jan 3, 2012

Filed:

Feb 28, 2011

Appl. No.:

13/036807

Inventors:

Dale G. Wilson - Kuna ID, US

Assignee:

American Semiconductor, Inc. - Boise ID

International Classification:

H01L 29/80

US Classification:

257278

Abstract:

Memory cells are constructed from double-gated four terminal transistors having independent gate control. DRAM cells may use one, two or three transistors. Single transistor cells are constructed either with or without a bit storage capacitor, and both NAND- and NOR-type Non-Volatile NVRAM cells, as well as Ferroelectric FeRAM cells, are described. For all cells, top gates provide conventional access while independent bottom gates provide control to optimize memory retention for given speed and power parameters as well as to accommodate hardening against radiation. In a single transistor cell without a capacitor, use of the bottom gate allows packing to a density approaching 2 F. The memory cells are compatible with SOI logic circuitry for use as embedded RAM in SOC applications.

US Patent:

8148759, Apr 3, 2012

Filed:

Feb 28, 2011

Appl. No.:

13/036735

Inventors:

Dale G. Wilson - Kuna ID, US

Assignee:

American Semiconductor, Inc. - Boise ID

International Classification:

H01L 29/80

US Classification:

257278

Abstract:

Memory cells are constructed from double-gated four terminal transistors having independent gate control. DRAM cells using one transistor to implement a Ferroelectric FeRAM are described. Top gates provide conventional access while independent bottom gates provide control to optimize memory retention for given speed and power parameters as well as to accommodate hardening against radiation. In a single transistor cell without a capacitor, use of the bottom gate allows packing to a density approaching 2 F. Using a ferroelectric material as the gate insulator produces a single-transistor FeRAM cell that overcomes the industry-wide Write Disturb problem. The memory cells are compatible with SOI logic circuitry for use as embedded RAM in SOC applications.

US Patent:

20140264938, Sep 18, 2014

Filed:

Mar 14, 2014

Appl. No.:

14/213417

Inventors:

Dale G. Wilson - Kuna ID, US

International Classification:

H01L 23/48

US Classification:

257774

Abstract:

The described Flexible Interconnect is useful for making electrical or other contact between various combinations of semiconductor die, printed circuit boards and other components. A thin flexible material, such as a polymer, supports printed lines that connect pads which may contain vias. The flexible interconnect can be attached using conductive and non-conductive epoxies to the components that are to be interconnected. Each interconnect can be individually insulated from adjacent interconnects, so that it can be deformed and flexed without making contact with another. The described interconnects can span long distances and conform to underlying topography. Metal interconnects may be used to conduct heat or to form heat sinks. Similarly, flexible interconnects may be formed from material that is an electrical insulator but thermally conductive in order to transport heat away from the attached circuitry. Optical conductors may be supported for use as flexible photonic waveguides.

US Patent:

20140224882, Aug 14, 2014

Filed:

Feb 14, 2014

Appl. No.:

14/181539

Inventors:

Dale G. Wilson - Kuna ID, US

International Classification:

G06K 19/077

US Classification:

235488, 235492

Abstract:

This smart card transponder is made extremely flexible by being ultrathin. Its thickness of only 0.25 mm is achieved by using all ultrathin flexible substrates. A Semiconductor-on-Polymer (SOP) process creates flexible integrated circuit (IC) components which are applied to a flexible antenna substrate. With suitable selection of materials, no additional substrates are required. The antenna substrate may be a thin PVC or even paper. The antenna is printed directly onto the substrate using conductive ink. Passive components such as resistors, capacitors, inductors and delay lines are also formed from conductive ink as appropriate to the circuit being implemented. Interconnections between components are created in a similar process. The ultrathin SOP ICs require no bonding wires since their contact pads are readily accessible for attachment to the interconnects through conductive epoxy. Extreme flexibility of all componentry enhances reliability while enabling inclusion of larger, more complex ICs.

US Patent:

20140219604, Aug 7, 2014

Filed:

Feb 4, 2014

Appl. No.:

14/172724

Inventors:

Dale G. Wilson - Kuna ID, US

International Classification:

G02B 6/12

US Classification:

385 14, 438 31

Abstract:

Three-dimensional flexible photonic integrated circuits on silicon are fabricated in semiconductor wafer form and then transferred to Silicon-on-Polymer (SOP) substrates. SOP provides flexibility for conformal mounting with devices capable of maintaining performance when dynamically deformed to allow routing of light in x, y and z directions. Bonding a wafer or individual die of III-V semiconductor, such as Gallium Arsenide or similar photonic material, to the flexible silicon creates an active region for lasers, amplifiers, modulators, and other photonic devices using standard processing. Mounting additional photonic devices to the opposite side of a flexible photonic waveguide produces a stack for three-dimensional devices. Multiple flexible photonic waveguides may be stacked to increase functionality by transferring light between stacked waveguides. The flexible photonic circuit allows for integration of photonic devices such as low threshold lasers, tunable lasers, and other photonic integrated circuits with flexible Complementary Metal Oxide Semiconductor (CMOS) integrated circuits.