Daniel T Liu

US Patent:

7515049, Apr 7, 2009

Filed:

Jun 8, 2006

Appl. No.:

11/449084

Inventors:

Arun Sharma - Cupertino CA, US
Daniel Fritschen - Sunnyvale CA, US
Daniel Liu - San Francisco CA, US
Norma Riley - Fremont CA, US

Assignee:

Asyst Technologies, Inc. - Fremont CA

International Classification:

G08B 13/14

US Classification:

3405726, 3405721, 340 101

Abstract:

The present invention generally comprises an apparatus that allows an RFID antenna to obtain information from an RFID tag mounted on a container. The apparatus reproduces the RF field generated by the antenna to a location proximate to the RFID tag. In one embodiment, the apparatus comprises a pickup device and a reproduction device electrically coupled with the pickup device. In another embodiment, the apparatus comprises at least one magnetic rod, which creates a magnetic path for the RF field to travel between the antenna and the RFID tag. In another embodiment, the apparatus comprises a pickup antenna and a reproduction antenna for transmitting the RF signal from the antenna proximate to the RFID tag.

US Patent:

7884433, Feb 8, 2011

Filed:

Oct 31, 2008

Appl. No.:

12/290495

Inventors:

Tom Zhong - Saratoga CA, US
Rongfu Xiao - Fremont CA, US
Adam Zhong - Milpitas CA, US
Wai-Ming Johnson Kan - San Ramon CA, US
Daniel Liu - San Jose CA, US

Assignee:

MagIC Technologies, Inc. - Milpitas CA

International Classification:

H01L 29/82

US Classification:

257421, 257774, 257E29323, 257E23145

Abstract:

A STT-MRAM integration scheme is disclosed wherein the connection between a MTJ and CMOS metal is simplified by forming an intermediate via contact (VAC) on a CMOS landing pad, a metal (VAM) pad that contacts and covers the VAC, and a MTJ on the VAM. A dual damascene process is performed to connect BIT line metal to CMOS landing pads through VAC/VAM/MTJ stacks in a device region, and to connect BIT line connection pads to CMOS connection pads through BIT connection vias outside the device region. The VAM pad is a single layer or composite made of Ta, TaN, or other conductors which serves as a diffusion barrier, has a highly smooth surface for MTJ formation, and provides excellent selectivity with refill dielectric materials during a chemical mechanical polish process. Each VAC is from 500 to 3000 Angstroms thick to minimize additional circuit resistance and minimize etch burden.

US Patent:

7919407, Apr 5, 2011

Filed:

Nov 17, 2009

Appl. No.:

12/590945

Inventors:

Tom Zhong - Saratoga CA, US
Wai-Ming Johnson Kan - San Ramon CA, US
Daniel Liu - San Jose CA, US
Adam Zhong - Milpitas CA, US

Assignee:

MagIC Technologies, Inc. - Milpitas CA

International Classification:

H01L 21/4763

US Classification:

438622, 438 3, 438614, 438618, 438620, 438674, 257E21665

Abstract:

Described herein are novel, cost effective and scalable methods for integrating a CMOS level with a memory cell level to form a field induced MRAM device. The memory portion of the device includes N parallel word lines, which may be clad, overlaid by M parallel bit lines orthogonal to the word lines and individual patterned memory cells formed on previously patterned electrodes at the N×M intersections of the two sets of lines. The memory portion is integrated with a CMOS level and the connection between levels is facilitated by the formation of interconnecting vias between the N×M electrodes and corresponding pads in the CMOS level and by word line connection pads in the memory device level and corresponding metal pads in the CMOS level. Of particular importance are process steps that replace single damascene formations by dual damascene formations, different process steps for the formation of clad and unclad word lines and the formation of patterned electrodes for the memory cells prior to the patterning of the cells themselves.

US Patent:

8183061, May 22, 2012

Filed:

Feb 7, 2011

Appl. No.:

12/931648

Inventors:

Tom Zhong - Saratoga CA, US
Rongfu Xiao - Fremont CA, US
Adam Zhong - Milpitas CA, US
Wai-Ming Johnson Kan - San Ramon CA, US
Daniel Liu - San Jose CA, US

Assignee:

MagIC Technologies, Inc. - Milpitas CA

International Classification:

H01L 21/441

US Classification:

438 3, 257421, 257E21577, 257E21579, 438637

Abstract:

A STT-MRAM integration scheme is disclosed wherein the connection between a MTJ and CMOS metal is simplified by forming an intermediate via contact (VAC) on a CMOS landing pad, a metal (VAM) pad that contacts and covers the VAC, and a MTJ on the VAM. A dual damascene process is performed to connect BIT line metal to CMOS landing pads through VAC/VAM/MTJ stacks in a device region, and to connect BIT line connection pads to CMOS connection pads through BIT connection vias outside the device region. The VAM pad is a single layer or composite made of Ta, TaN, or other conductors which serves as a diffusion barrier, has a highly smooth surface for MTJ formation, and provides excellent selectivity with refill dielectric materials during a chemical mechanical polish process. Each VAC is from 500 to 3000 Angstroms thick to minimize additional circuit resistance and minimize etch burden.

US Patent:

8324698, Dec 4, 2012

Filed:

Jan 4, 2011

Appl. No.:

12/930333

Inventors:

Tom Zhong - Saratoga CA, US
Rongfu Xiao - Fremont CA, US
Adam Zhong - Milpitas CA, US
Wai-Ming Johnson Kan - San Ramon CA, US
Daniel Liu - San Jose CA, US

Assignee:

MagIC Technologies, Inc. - Milpitas CA

International Classification:

H01L 29/82

US Classification:

257421, 257774, 257E29323, 257E23145

Abstract:

A STT-MRAM integration scheme is disclosed wherein the connection between a MTJ and CMOS metal is simplified by forming an intermediate via contact (VAC) on a CMOS landing pad, a metal (VAM) pad that contacts and covers the VAC, and a MTJ on the VAM. A dual damascene process is performed to connect BIT line metal to CMOS landing pads through VAC/VAM/MTJ stacks in a device region, and to connect BIT line connection pads to CMOS connection pads through BIT connection vias outside the device region. The VAM pad is a single layer or composite made of Ta, TaN, or other conductors which serves as a diffusion barrier, has a highly smooth surface for MTJ formation, and provides excellent selectivity with refill dielectric materials during a chemical mechanical polish process. Each VAC is from 500 to 3000 Angstroms thick to minimize additional circuit resistance and minimize etch burden.

US Patent:

8456883, Jun 4, 2013

Filed:

May 29, 2012

Appl. No.:

13/482157

Inventors:

Daniel Liu - San Jose CA, US

Assignee:

Headway Technologies, Inc. - Milpitas CA

International Classification:

H01L 21/8239
G11C 5/08
G11C 11/15
H01L 21/8234
H01L 27/22

US Classification:

365 66, 365158, 365171, 257369, 257E27108, 257E21665, 257E21627, 438 3, 438200

Abstract:

CMOS devices are provided in a substrate having a topmost metal layer comprising metal landing pads and metal connecting pads. A plurality of magnetic tunnel junction (MTJ) structures are provided over the CMOS devices and connected to the metal landing pads. The MTJ structures are covered with a dielectric layer that is polished until the MTJ structures are exposed. Openings are etched in the dielectric layer to the metal connecting pads. A seed layer is deposited over the dielectric layer and on inside walls and bottom of the openings. A copper layer is plated on the seed layer until the copper layer fills the openings. The copper layer is etched back and the seed layer is removed. Thereafter, an aluminum layer is deposited over the dielectric layer, contacting both the copper layer and the MTJ structures, and patterned to form a bit line.

US Patent:

20200356482, Nov 12, 2020

Filed:

May 7, 2019

Appl. No.:

16/405691

Inventors:

- Santa Clara CA, US
Jeffrey Baxter - Cupertino CA, US
Sai Prashanth Muralidhara - Portland OR, US
Sharada Venkateswaran - San Francisco CA, US
Daniel Liu - Walnut Creek CA, US
Nishant Singh - Bengaluru, IN
Bahaa Fahim - Santa Clara CA, US
Samuel D. Strom - Folsom CA, US

International Classification:

G06F 12/0817

Abstract:

A processor includes one or more cores having cache, a cache home agent (CHA), a near memory controller, to near memory, and a far memory controller, which is to: receive a first memory read operation from the CHA directed at a memory address; detect a miss for the first memory address at the near memory; issue a second memory read operation to the far memory controller to retrieve a cache line, having first data, from the memory address of far memory; receive the cache line from the far memory controller in response to the second memory read operation; and send the cache line to the CHA with a forced change to a directory state of the cache line at the CHA, the forced change to cause the CHA to snoop remote sockets to maintain data coherence for the cache line in an absence of directory state in the far memory.

US Patent:

20200201697, Jun 25, 2020

Filed:

Dec 21, 2018

Appl. No.:

16/230020

Inventors:

- Milpitas CA, US
Daniel H. LIU - San Jose CA, US
Wenhan Zhang - Mississauga, CA
Hualiang Yu - San Jose CA, US

Assignee:

Gyrfalcon Technology Inc. - Milpitas CA

International Classification:

G06F 11/07
G11C 29/18
G06N 3/063
G11C 29/44

Abstract:

This disclosure relates to testing of integrated artificial intelligence (AI) circuit with embedded memory to improve effective chip yield and to mapping addressable memory segments of the embedded memory to multilayer AI networks at the network level, layer level, parameter level, and bit level based on bit error rate (BER) of the addressable memory segments. The disclosed methods and systems allows for deployment of one or more multilayer AI networks in an AI circuit with sufficient model accuracy even when the embedded memory has an overall BER higher than a preferred overall threshold.