Daniel P Mclaughlin

US Patent:

6571348, May 27, 2003

Filed:

Jul 20, 1999

Appl. No.:

09/357698

Inventors:

Terry T. Tsai - San Jose CA
Daniel F. McLaughlin - Santa Clara CA

Assignee:

Genesis Semiconductor, Inc. - San Jose CA

International Classification:

G06F 1100

US Classification:

714 6, 711133

Abstract:

A look ahead column redundancy circuit provides high speed memory access to both regular memory arrays and redundant memory arrays. In the preferred embodiment of the present invention, the information on both the address bus and the information on the next address bus are decoded by redundant column decoders in parallel. The decoded information from the redundant column decoders is then provided to a redundancy column pathway as the addressing information from the address bus and the next address bus is provided to a main column pathway. The information on the address bus is latched when beginning at a new column address. The information on the next address bus is latched for the next column address when operating in a burst cycle mode. The main column pathway preferably includes a latch, a main column decoder and a main column select circuit. A disable signal is also activated by the redundant column decoders if the addressing information for a current memory access operation corresponds to an address within the redundant memory array.

US Patent:

62085697, Mar 27, 2001

Filed:

Jul 20, 1999

Appl. No.:

9/356805

Inventors:

Vipul Patel - San Jose CA
Daniel F. McLaughlin - Santa Clara CA
Terry T. Tsai - San Jose CA

Assignee:

Genesis Semiconductor, Inc. - San Jose CA

International Classification:

G11C13/00

US Classification:

365200

Abstract:

An apparatus for sharing redundancy circuits between memory arrays within a semiconductor memory device includes at least two main memory arrays comprised of a plurality of memory cells aligned in rows and/or columns and a shared redundancy circuit. The redundancy circuits preferably include a plurality of redundancy rows and a redundancy decoder which is configured for accessing the redundancy rows whenever a read or write operation involves use of a defective row within the main memory arrays for which a redundant row has been substituted. Preferably, each main memory array has access to the shared redundancy circuit. The shared redundancy circuit is used for substituting defective rows within a corresponding main memory array. The shared redundancy circuit provides extra redundant capacity to both of the main memory arrays.

US Patent:

61412759, Oct 31, 2000

Filed:

Jul 20, 1999

Appl. No.:

9/357739

Inventors:

Terry T. Tsai - San Jose CA
Daniel F. McLaughlin - Santa Clara CA

Assignee:

Genesis Semiconductor - San Jose CA

International Classification:

G11C 700

US Classification:

365203

Abstract:

An equalization and precharge circuit precharges and equalizes local input/output (LIO) signal lines between each memory access operation within a memory circuit. The equalization and precharge circuit includes a local voltage circuit which maintains the level of the LIO signal lines at a standby voltage level during standby periods. Preferably, the standby voltage level is approximately equal to half of the supply voltage VCC. Separate precharge and equalization circuits are included to precharge and equalize the LIO signal lines between memory access operations. During precharge periods, a precharge control signal LIOPC is preferably at a logical high voltage level for a predetermined period of time between memory access operations, thereby forming a fixed-width pulse and raising the LIO signals to a known precharge level. The LIO signal lines are charged to a known level equal to the standby voltage level plus a voltage V(t) during the precharge and equalization period. The voltage V(t) is dependent on the duration of the fixed-width pulse of the precharge control signal LIOPC.