Daniel D Xu

US Patent:

6404665, Jun 11, 2002

Filed:

Sep 29, 2000

Appl. No.:

09/675803

Inventors:

Tyler A. Lowrey - San Jose CA
Daniel Xu - Mountain View CA
Chien Chiang - Fremont CA
Patrick J. Neschleba - San Carlos CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 1100

US Classification:

365100, 365148, 365163, 257 3, 257 4, 257 5

Abstract:

An apparatus comprising a volume of memory material and a pair of spacedly disposed conductors. An electrode coupled to the volume of memory material and disposed between the volume of memory material and one conductor comprises a first material having a first resistivity value and a second material having a different second resistivity value formed by exposing the first material to a gaseous ambient.

US Patent:

6437383, Aug 20, 2002

Filed:

Dec 21, 2000

Appl. No.:

09/745322

Inventors:

Daniel Xu - Mountain View CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 2972

US Classification:

257300, 257 2, 257110, 257121, 257124, 257192, 257246, 257295, 257296, 257350

Abstract:

The invention relates to a phase-change memory device. The device includes a double-trench isolation structure around the diode stack that communicates to the lower electrode. The present invention also relates to a method of making a phase-change memory device. The method includes forming two orthogonal and intersecting isolation trenches around a memory cell structure diode stack.

US Patent:

6462984, Oct 8, 2002

Filed:

Jun 29, 2001

Appl. No.:

09/895599

Inventors:

Daniel Xu - Mountain View CA
Tyler A. Lowrey - San Jose CA
David L. Kencke - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 1136

US Classification:

365175, 365174, 365163, 365148, 365203, 3652257, 365 51

Abstract:

An integrated circuit (IC) has a number of memory cells, each of which has a diode structure coupled between a bitline and a wordline that are selected when programming that cell. A target memory cell of the IC is programmed while simultaneously floating a number of unselected bitlines and wordlines in the IC.

US Patent:

6566700, May 20, 2003

Filed:

Oct 11, 2001

Appl. No.:

09/975272

Inventors:

Daniel Xu - Mountain View CA

Assignee:

Ovonyx, Inc. - Boise ID

International Classification:

H01L 27108

US Classification:

257296, 257 4, 257 77, 257614, 257734

Abstract:

A phase-change memory cell may be formed with a carbon-containing interfacial layer that heats a phase-change material. By forming the phase-change material in contact, in one embodiment, with the carbon containing interfacial layer, the amount of heat that may be applied to the phase-change material, at a given current and temperature, may be increased. In some embodiments, the performance of the interfacial layer at high temperatures may be improved by using a wide band gap semiconductor material such as silicon carbide.

US Patent:

6514805, Feb 4, 2003

Filed:

Jun 30, 2001

Appl. No.:

09/896532

Inventors:

Daniel Xu - Mountain View CA
Erman Bengu - San Jose CA
Ming Jin - San Jose CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 2100

US Classification:

438164, 438405, 438427, 438703

Abstract:

A method comprising forming a first trench in a substrate, and forming a second trench in the substrate, the second trench intersecting the first trench and having a retrograde sidewall profile relative to a direction from a top of the trench to a bottom of the trench. An apparatus comprising a matrix of cells in a substrate formed by a plurality of first trenches and a plurality of second trenches, the plurality of second trenches intersecting the plurality of first trenches and having a retrograde sidewall profile relative to a direction from a top to a bottom of the respective trench; and an electrically accessible storage device coupled to respective ones of the matrix of cells.

US Patent:

6563164, May 13, 2003

Filed:

Feb 8, 2001

Appl. No.:

09/780805

Inventors:

Tyler A. Lowrey - San Jose CA
Daniel Xu - Mountain View CA
Chien Chiang - Fremont CA
Patrick J. Neschleba - San Carlos CA

Assignee:

Ovonyx, Inc. - Boise ID

International Classification:

H01L 4700

US Classification:

257314, 257 5

Abstract:

An apparatus comprising a volume of memory material and a pair of spacedly disposed conductors. An electrode coupled to the volume of memory material and disposed between the volume of memory material and one conductor comprises a first material having a first resistivity value and a second material having a different second resistivity value formed by exposing the first material to a gaseous ambient.

US Patent:

6642102, Nov 4, 2003

Filed:

Jun 30, 2001

Appl. No.:

09/896530

Inventors:

Daniel Xu - Mountain View CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21336

US Classification:

438257, 438396, 438 95, 438470, 438128, 257 3, 257530, 257621

Abstract:

A method comprising forming as stacked materials on a substrate, a volume of programmable material and a signal line, conformably forming a first dielectric material on the stacked materials, forming a second dielectric material on the first material, etching an opening in the second dielectric material with an etchant that, between the first dielectric material and the second dielectric material, favors removal of the second dielectric material, and forming a contact in the opening to the stacked materials. An apparatus comprising a contact point formed on a substrate, a volume of programmable material formed on the contact point, a signal line formed on the volume of programmable material, a first dielectric material conformally formed on the signal line, a different second dielectric material formed on the first dielectric material, and a contact formed through the first dielectric material and the second dielectric material to the signal line.

US Patent:

6667900, Dec 23, 2003

Filed:

Dec 28, 2001

Appl. No.:

10/034331

Inventors:

Tyler Lowrey - San Jose CA
Daniel Xu - Mountain View CA

Assignee:

Ovonyx, Inc. - Boise ID

International Classification:

G11C 1115

US Classification:

365171, 365173

Abstract:

Briefly, in accordance with an embodiment of the invention, a method and an apparatus to read a phase change memory is provided, wherein the method includes zero biasing unselected memory cells during reading of a selected memory cell.