Daniel H Xu

US Patent:

20010024857, Sep 27, 2001

Filed:

May 23, 2001

Appl. No.:

09/865006

Inventors:

Krishna Parat - Palo Alto CA, US
Raghupathy Giridhar - Saratoga CA, US
Cheng Hu - San Jose CA, US
Daniel Xu - Mountain View CA, US
Yudong Kim - Santa Clara CA, US
Glen Wada - Fremont CA, US

International Classification:

H01L021/336

US Classification:

438/259000, 438/257000, 438/262000, 438/263000

Abstract:

A method of fabricating a flash memory integrated circuit is described. In an embodiment of the present invention a dielectric filled trench isolation region is formed in a silicon substrate. The dielectric filled trench isolation region isolates a first portion of the silicon substrate from a second portion of the silicon substrate. A portion of the dielectric in the trench is then removed to reveal a portion of the silicon substrate in the trench between the first and second portions of the silicon substrate. Ions are then implanted to form a first source region in the first portion of the silicon substrate and to form a second source region in the second portion of the silicon substrate and to form a doped region in the revealed silicon substrate in the trench wherein the doped region in the trench extends from the first doped source region to the second doped source region.

US Patent:

62652923, Jul 24, 2001

Filed:

Jul 12, 1999

Appl. No.:

9/351498

Inventors:

Krishna Parat - Palo Alto CA
Raghupathy V. Giridhar - Sratoga CA
Cheng C. Hu - San Jose CA
Daniel Xu - Mountain View CA
Yudong Kim - Santa Clara CA
Glen Wada - Fremont CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21425

US Classification:

438524

Abstract:

A method of fabricating a flash memory integrated circuit is described. In an embodiment of the present invention a dielectric filled trench isolation region is formed in a silicon substrate. The dielectric filled trench isolation region isolates a first portion of the silicon substrate from a second portion of the silicon substrate. A portion of the dielectric in the trench is then removed to reveal a portion of the silicon substrate in the trench between the first and second portions of the silicon substrate. Ions are then implanted to form a first source region in the first portion of the silicon substrate and to form a second source region in the second portion of the silicon substrate and to form a doped region in the revealed silicon substrate in the trench wherein the doped region in the trench extends from the first doped source region to the second doped source region.