David E Bockelman

US Patent:

6510191, Jan 21, 2003

Filed:

Feb 9, 2001

Appl. No.:

09/780077

Inventors:

David E. Bockelman - Weston FL

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H04L 700

US Classification:

375371, 327269, 455260, 708271, 713401

Abstract:

A digital frequency synthesizer includes a clock which produces a clock signal oscillating at a fixed frequency and a delay line which receives the clock signal and which produces therefrom a plurality of phase shifted clock signals oscillating at the fixed frequency. Each phase shifted clock signal is shifted in phase with respect to the clock signal and with respect to the other phase shifted clock signals. A look-up table receives an address value related to an ideal phase shifted clock signal oscillating at the fixed frequency and outputs a tap address related to the address value. A selection circuit receives the plurality of phase shifted clock signals and the tap address and outputs one of the phase shifted clock signals in response thereto. A sampling circuit samples at least a portion of the one phase shifted clock signal output by the selection circuit and outputs the sampled portion to form at least a part of an oscillator signal having a desired frequency.

US Patent:

6539344, Mar 25, 2003

Filed:

Apr 21, 2000

Appl. No.:

09/553814

Inventors:

Robert E. Stengel - Pompano Beach FL
David E. Bockelman - Weston FL

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 760

US Classification:

703 2, 703 14, 702 57, 716 4, 324612, 324638

Abstract:

A parameter extraction technique for an electrical structure is based on a definition of network parameters that isolates pure mode responses of the electrical structure, and that makes mode conversion responses of the electrical structure negligible. A set of network parameters is obtained that represents pure mode responses for the electrical structure ( ). These network parameters are processed to obtain model parameters that characterize each pure mode response ( ). Preferably, the mode specific parameters to combined to obtain mode independent parameters, such as coupling factor, propagation constant, and characteristic impedance values ( ).

US Patent:

6603964, Aug 5, 2003

Filed:

Sep 5, 2000

Appl. No.:

09/655318

Inventors:

Matthew D. Rowley - Weston FL
David E. Bockelman - Weston FL

Assignee:

Motorola, Inc. - Schamburg IL

International Classification:

H04B 128

US Classification:

455333, 455326, 327210

Abstract:

A mixer circuit ( ) includes two balanced transmission gate mixers ( ). The mixer circuit ( ) balances charge injection mechanisms which reduces carrier feedthrough in the preferred embodiment. The inputs signals provided to the second transmission gate mixer ( ) are reversed as compared to those provided to the first transmission gate mixer ( ). By reversing the forward path through the second transmission gate mixer ( ), charge injection parasitics seen by the first transmission gate mixer ( ) are canceled by those in the second transmission gate mixer ( ).

US Patent:

7154978, Dec 26, 2006

Filed:

Nov 2, 2001

Appl. No.:

10/000914

Inventors:

Jui-Kuo Juan - Coral Springs FL, US
Robert E. Stengel - Pompano Beach FL, US
Frederick J. Martin - Plantation FL, US
David E. Bockelman - Dripping Springs TX, US

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03D 3/24

US Classification:

375376, 327149

Abstract:

A delay locked loop frequency synthesizer in several embodiments uses a primary delay line element () and one or more secondary delay elements (). In one embodiment, a main delay line () is used to coarsely select a frequency output while a secondary delay element (), either passive or active, is used to increase the resolution of the primary delay line (). In the passive embodiment, a coarse and fine frequency selection is possible by selecting components from the output taps of the main delay line () as a driving signal for the passive secondary delay element () to provide the coarse adjustment and selecting an output from the secondary delay element () to provide the fine selection.

US Patent:

7162000, Jan 9, 2007

Filed:

Jan 16, 2002

Appl. No.:

10/050233

Inventors:

Robert E. Stengel - Pompano Beach FL, US
Joseph P. Heck - Ft. Lauderdale FL, US
David E. Bockelman - Dripping Springs TX, US

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03D 3/24
H03C 5/00
H03L 7/00
H03L 7/06

US Classification:

375373, 375268, 375271, 375320, 375322, 375300, 375302, 327141, 327152, 327153, 327154, 327155

Abstract:

A delay locked loop circuit () in which multiple outputs are produced. A single delay line () is shared among multiple tap selection circuits (A, B, C). Fixed phase shifts () can be introduced between multiple outputs. A modulating signal can be used in the tap selection processing to produce digital amplitude, frequency and/or phase modulation.

US Patent:

7728661, Jun 1, 2010

Filed:

May 5, 2008

Appl. No.:

12/151199

Inventors:

David E. Bockelman - Dripping Springs TX, US
Vishnu Srinivasan - Austin TX, US

Assignee:

Javelin Semiconductor, Inc. - Austin TX

International Classification:

H03F 1/14
H03F 3/68

US Classification:

330 51, 330124 R, 330195

Abstract:

In one embodiment, the present invention includes multiple gain stages and an output network coupled to the gain stages. Each of the gain stages can be independently controlled to amplify a radio frequency (RF) signal to an output power level for transmission from a mobile wireless device. When controlled to be inactive, at least one of the gain stages can be placed into a low impedance state.

US Patent:

7760023, Jul 20, 2010

Filed:

Sep 29, 2006

Appl. No.:

11/536832

Inventors:

David Bockelman - Dripping Springs TX, US
Ryan M. Bocock - Austin TX, US
Susanne A. Paul - Austin TX, US
Timothy J. Dupuis - Austin TX, US

Assignee:

Black Sand Technologies, Inc. - Austin TX

International Classification:

H03F 3/45

US Classification:

330258, 330252, 330255, 330124 R, 330295, 455326

Abstract:

A method and apparatus is provided for use in power amplifiers for reducing the peak voltage that transistors are subjected to. A power amplifier is provided with first and second switching devices and an inductor connected between the switching devices. The switching devices are driven such that the switching devices are turned on and off during the same time intervals. Differential RF power amplifiers are also provided with inductive networks coupled at various nodes of the power amplifiers. In some examples, techniques are used to stabilize differential power amplifiers by stabilizing common-mode feedback loops.

US Patent:

7768350, Aug 3, 2010

Filed:

Dec 30, 2008

Appl. No.:

12/317819

Inventors:

Vishnu Srinivasan - Austin TX, US
David E. Bockelman - Dripping Springs TX, US

Assignee:

Javelin Semiconductor, Inc. - Austin TX

International Classification:

H03F 3/45

US Classification:

330253, 330258, 330276, 330195

Abstract:

In one embodiment, the present invention includes multiple gain stages to receive and amplify a differential input signal at different common mode voltages. The stages each may include a pair of linear NMOS gain transistors coupled to a primary coil of a given output transformer. One of the stages may include commonly coupled terminals coupled to a center tap of the primary coil of an output transformer of another stage, and a supply current provided to one of the stages is re-used for the other stage(s).