David Ray Erickson

US Patent:

7421637, Sep 2, 2008

Filed:

Jan 16, 2003

Appl. No.:

10/346353

Inventors:

David B. Erickson - Plano TX, US

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

G01R 31/28

US Classification:

714739

Abstract:

Generating test input includes initializing a current pseudo-random value at a test input generator coupled to a circuit component. Write data is received from the circuit component. The following are repeated to generate next pseudo-random values as test input. The current pseudo-random value and the write data are retrieved. A next pseudo-random value is generated from the current pseudo-random value and the write data according to a generation function. The next pseudo-random value is transferred to the circuit component as the test input.

US Patent:

59615753, Oct 5, 1999

Filed:

Feb 26, 1996

Appl. No.:

8/607057

Inventors:

Mark W. Hervin - Dallas TX
David B. Erickson - Plano TX

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G06F 738

US Classification:

708209

Abstract:

Circuit for performing arithmetic operations in a 32-bit architecture. The circuit includes a five stage shift and rotate circuit coupled between first and second 32-bit busses in the following sequence: an 8-bit shift and rotate circuit, a 16-bit shift and rotate circuit, a 1-bit shift and rotate circuit, a 2-bit shift and rotate circuit and a 4-bit shift and rotate circuit. For double word sized (32-bit) operands, the variously sized shift and rotate circuits may be selectively enabled to perform between 1-bit and 31-bit shift/rotate/pass operations. For byte sized operands, the 8-bit and 16-bit shift and rotate circuits are used to pre-process the operands while the 1-bit, 2-bit and 4-bit shift and rotate circuits are selectively enabled to perform the full range, i. e. , 1-bit to 7-bit, of possible shift/rotate operations. For word sized (16-bit) operands, the 16-bit or 8-bit and 16-bit shift and rotate circuits are used to pre-process the operands while the 1-bit, 2-bit and 4-bit shift and rotate circuits are selectively enabled to perform the full range of shift/rotate operations.