David Philip Lerner

US Patent:

7023604, Apr 4, 2006

Filed:

Mar 17, 2001

Appl. No.:

09/812066

Inventors:

Behrang Behin - Berkeley CA, US
Robert Conant - Berkeley CA, US
Michael J. Daneman - Pacifica CA, US
David Horsley - Berkeley CA, US
Meng-Hsiung Kiang - Berkeley CA, US
David Lerner - Corte Madera CA, US
Satinderpall Pannu - Berkeley CA, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

C02B 26/00
C02B 26/08
C02B 6/26

US Classification:

359290, 359226, 385 17, 385 18

Abstract:

A beam steering module comprised of a mirror stack array in close proximity to a collimator array controllably steers photons along two axis and in a direction substantially less than 90 degrees to the collimator orientation. Several configurations of the module are described using single and double axis mirror rotation and relay optics. Optical telecommunications switches are shown using modules coupled to each other along flat and curved surfaces, with and without use of fold mirror and enabling a plurality of configuration options including photodetector optical power monitoring schemes that require no external power taps.

US Patent:

20190384348, Dec 19, 2019

Filed:

Feb 24, 2017

Appl. No.:

16/480830

Inventors:

- Santa Clara CA, US
Krishnakanth V. SISTLA - Beaverton OR, US
Corey D. GOUGH - Portland OR, US
Ian M. STEINER - Portland OR, US
Nikhil GUPTA - Porltand OR, US
Vivek GARG - Folsom CA, US
Ankush VARMA - Hillsboro OR, US
Sujal A. VORA - San Jose CA, US
David P. LERNER - Oakland CA, US
Joseph M. SULLIVAN - Santa Clara CA, US
Nagasubramanian GURUMOORTHY - Portland OR, US
William J. BOWHILL - Framingham MA, US
Venkatesh RAMAMURTHY - Portland OR, US
Chris MACNAMARA - Limerick, IE
John J. BROWNE - Limerick, IE
Ripan DAS - Beaverton OR, US

International Classification:

G06F 1/08
G06F 1/3203
G06F 9/30
G06F 9/455

Abstract:

A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.

US Patent:

20170168753, Jun 15, 2017

Filed:

Dec 11, 2015

Appl. No.:

14/966270

Inventors:

- Alameda CA, US
David M. LERNER - Alameda CA, US

International Classification:

G06F 3/06

Abstract:

A device and method generates a graphical representation for memory leak detection. The method includes executing a selected application for a time period. The method includes determining a plurality of memory application programming interface (API) functions performed during the execution of the selected application in the time period. Each of the memory API functions request a chunk of a memory of the electronic device at a specified time. The method includes determining select ones of the memory API functions that do not release the respective chunk of the memory in the time period. The method includes generating the graphical representation including the selected memory API functions at the respective specified time for identification of a memory leak of the selected application.