David E Liu

US Patent:

6360457, Mar 26, 2002

Filed:

Jun 28, 2000

Appl. No.:

09/607516

Inventors:

Yi-Ming Qui - City of Industry CA 91748
David Liu - City of Industry CA 91748
Joanne Yang - City of Industry CA 91748

International Classification:

A61F 514

US Classification:

36140, 36136, 36141, 36 43, 600 15

Abstract:

A health care shoe, which can continuously provide adequate magnetic field arranged to penetrate through the wearers foot for improving the wearers blood circulation and metabolism, includes a sole; an insole placed on top the sole, which has a plurality of magnet cavities formed and distributed thereon; a shoe body rigidly attached on top of the sole to define a foot chamber between the shoe body and the insole; a plurality of base magnet elements fittingly received in the magnet cavities respectively provided on the insole; and a plurality of upper magnet elements embedded inside the shoe body with respect to the positions of the base magnet elements located on the insole, wherein each of the upper magnet elements is arranged to constitute a transversal magnetic field penetrating through the foot chamber and flowing towards one of the base magnet elements. Moreover, the sole further has at least a medicine receiving cavity to receive a medicine unit which contains a medicine tablet made of painkiller or Chinese medical herb being incased therein. The medicine unit further includes a bottom magnet element positioned thereunder so as to produce magnetic filed around the medicine unit.

US Patent:

6398562, Jun 4, 2002

Filed:

Sep 17, 1999

Appl. No.:

09/398984

Inventors:

Michael J. Butler - San Francisco CA
Thomas E. Conn - Palo Alto CA
David M. Liu - Los Altos CA
Norman A. Parris - Belmont CA
Michael Reidy - Half Moon Bay CA
Pravin L. Soni - Sunnyvale CA

Assignee:

Cygnus, Inc. - Redwood City CA

International Classification:

H01R 458

US Classification:

439 91, 439909, 439725, 439596

Abstract:

Devices and methods are described for improving the contact of a conductive material, for example, a hydrogel, with a sensor, for example an electrode, by means of using mechanical force to apply the conductive material to the sensor before use of the conductive material and sensor in a sampling device. The device and methods of the present invention improve the sensor response characteristics in transdermal sampling devices placed in operative contact with a skin or mucosal surface of a biological system to obtain a chemical signal associated with an analyte of interest.

US Patent:

6596617, Jul 22, 2003

Filed:

Jun 22, 2000

Appl. No.:

09/602658

Inventors:

David K.Y. Liu - Fremont CA

Assignee:

Progressant Technologies, Inc. - Fremont CA

International Classification:

H01L 2128

US Classification:

438606, 438141, 438237, 438 60, 438 52

Abstract:

A method of making an n-channel metal-insulator-semiconductor field-effect transistor (MISFET) that exhibits negative differential resistance in its output characteristic (drain current as a function of drain voltage) is disclosed. By implanting ions into a substrate that is later thermally oxidized, a number of temporary charge trapping sites can be established above a channel region of a transistor. The channel is also heavily doped, so that a strong electrical field can be generated to accelerate hot carriers into the temporary charge trapping sites. The insulating layer formed during the oxidation step is made sufficiently thick to prevent quantum tunnelingo of the hot carriers into a gate electrode. Other suitable and conventional processing steps are used to finalize completion of the fabrication of the NDR device so that the entire process is compatible and achieved with CMOS processing techniques.

US Patent:

6711063, Mar 23, 2004

Filed:

Oct 3, 2002

Appl. No.:

10/264203

Inventors:

Anders T. Dejenfelt - Palo Alto CA
David Kuan-Yu Liu - Fremont CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G11C 1606

US Classification:

36518521, 365 51, 365 63

Abstract:

An EEPROM memory cell array architecture ( ) that substantially eliminates leakage current to allow for reading memory cells ( ) in a memory cell array of, for example, a CPLD at lower voltages than are possible with prior art architectures, thereby facilitating development of low voltage applications. This is accomplished by associating each wordline of the memory cell array with a ground transistor ( ). On one embodiment, the ground transistor ( ) can be a high voltage transistor, in which case the same high voltage control signal can control both the ground transistor ( ) and the memory cell=s read transistor ( ). In another embodiment, the ground transistor ( ) is a low voltage transistor controlled by a separate low voltage control signal.

US Patent:

6835979, Dec 28, 2004

Filed:

Jun 12, 2000

Appl. No.:

09/591968

Inventors:

David K. Liu - Fremont CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H01L 29788

US Classification:

257321, 438255, 36518514

Abstract:

A nonvolatile memory cell which is highly scalable includes a cell formed in a triple well. A select transistor can have a source which also acts as the emitter of a lateral bipolar transistor. The lateral bipolar transistor operates as a charge injector. The charge injector provides electrons for substrate hot electron injection of electrons onto the floating gate for programming. The cell depletion/inversion region may be extended by forming a capacitor as an extension of the control gate over the substrate between the source and channel of said sense transistor.

US Patent:

7091077, Aug 15, 2006

Filed:

Jun 7, 2005

Appl. No.:

11/146514

Inventors:

David Kuan-Yu Liu - Fremont CA, US
Jonathan Cheang-Whang Chang - Mountain View CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H01L 21/336

US Classification:

438197, 257E21327, 257E21623

Abstract:

Polysilicon or other material is directionally trimmed using two layers of photoresist and a photoresist etching process, such as ashing. A first layer of photoresist is patterned on a wafer. Portions of the first patterned photoresist are covered with a second layer of photoresist. The photoresist is trimmed to reduce the size of the exposed portions of the first patterned photoresist without reducing the size of the covered portions of the first patterned photoresist. The second layer of photoresist is removed. The selectively etched patterned first layer of photoresist is used as a process mask to define a structure in the underlying material. In a particular embodiment, the second photoresist covers endcap portions of gate photoresist. Directional trimming reduces the width of a polysilicon gate structure (i. e. gate length) over an active area of an FET, without reducing the length of original first patterned photoresist.

US Patent:

7535758, May 19, 2009

Filed:

Feb 6, 2007

Appl. No.:

11/703922

Inventors:

Albert Bergemont - Palo Alto CA, US
David Kuan-Yu Liu - Fremont CA, US
Venkatraman Prabhakar - Pleasanton CA, US

Assignee:

Maxim Integrated Products, Inc. - Sunnyvale CA

International Classification:

G11C 16/04

US Classification:

36518501, 365 94, 257315

Abstract:

Methods and apparatus, including computer program products, for a one or multiple-times programmable memory device. A semiconductor may include an active region of a substrate, a thin oxide layer over a substrate, a first and second polysilicon layer, and a first and second metal layer. The first polysilicon layer may have a floating gate, the active region may be substantially perpendicular to the floating gate, and the second polysilicon layer may include a control gate. The first metal layer may include a bit line connected to a first n-diffused region, where the bit line is substantially perpendicular to the floating gate. The second metal layer may include a word line and source line. The word line may be connected to the control gate, and the source line may be connected to a second n-diffused region. The thin gate oxide may have a thickness between 65 and 75 angstroms.

US Patent:

7713986, May 11, 2010

Filed:

Jun 15, 2006

Appl. No.:

11/455200

Inventors:

Todd W. Seeley - Moraga CA, US
David Y. Liu - Palo Alto CA, US
Stephen J. Klaus - San Francisco CA, US

Assignee:

FibroGen, Inc. - San Francisco CA

International Classification:

A61K 31/505

US Classification:

514269, 514 2

Abstract:

The invention relates to methods and compounds for treating chemotherapy-induced anemia. In particular, methods for treating chemotherapy-induced anemia in subjects refractory to treatment with recombinant human erythropoietin are encompassed herein.