David L Mccall

US Patent:

62790730, Aug 21, 2001

Filed:

Sep 30, 1999

Appl. No.:

9/410137

Inventors:

David E. McCracken - San Francisco CA
David L. McCall - Eau Claire WI

Assignee:

Silicon Graphics, Inc. - Mountain View CA

International Classification:

G06F 1200

US Classification:

711105

Abstract:

A configurable synchronizer (10) for DDR-SDRAM (12) is provided that includes a strobe select module (40) operable to receive a memory select signal (106) and to pass strobe signals (20, 30) from one or more DDR-SDRAMs (16, 18) to a number of synchronizer circuits (44) corresponding to data signals (17) passed in parallel by each DDR-SDRAM as indicated by the memory select signal (106). A rising edge latch (174) receives a rising edge data signal (170) and latches the rising edge data signal (170) through the rising edge latch (174) on a rising edge of the strobe signal (152). A falling edge latch (176) receives a falling edge data signal (172) and latches the falling edge data signal (172) through the falling edge latch (176) on a falling edge of the strobe signal (152). A data signal selector (180) receives a data order control signal (195) and forwards the rising edge data signal (170) from the rising edge latch (174) to an intermediate output (196) on either a rising edge of a memory clock cycle (193) or a falling edge of a memory clock cycle (193) followed by forwarding the falling edge data signal (172) from the falling edge latch (176) to the intermediate output (196) on an opposite edge of the memory clock cycle (193) in response to the data order control signal (195). An output latch (202) receives the intermediate output (196) and latches the intermediate output (196) through the output latch (202) to an output signal (154) on each core clock cycle (190).

US Patent:

51343126, Jul 28, 1992

Filed:

Apr 25, 1991

Appl. No.:

7/691454

Inventors:

Frederick J. Jones - Leominister MA
David L. McCall - Medway MA
John H. Hackenberg - Northboro MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

H03K 3289
H03K 19086

US Classification:

3072722

Abstract:

A bipolar ECL latch or flip-flop circuit of the isolated differential feedback type provides a high level of alpha particle immunity, without unduly affecting the propagation delay, power dissipation or circuit area in an integrated circuit device. A pair of latch transistors having differential input are used, with common emitters coupled to a clocked current source. The latch outputs are coupled back to a pair of holding transistors by two emitter follower feedback transistors. The holding transistors have a common emitter connection to a current source clocked inversely to that of the current source for the latch transistors, so the state of the latch is held by the holding transistors. The amplification of the feedback transistors is reduced so that the speed with which the transistor can react to transient noise such as that produced by an alpha hit is reduced. A shared current source is employed for the emitter follower feedback transistors to reduce the alpha particle sensitivity by lowering the feedback current without requiring two larger resistor values.

US Patent:

47854227, Nov 15, 1988

Filed:

Sep 15, 1986

Appl. No.:

6/907757

Inventors:

Dale F. Berndt - Plymouth MN
David L. McCall - Lake Elmo MN
Thomas R. Arneberg - Woodland Park CO

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G11C 1134
G11C 700
G11C 702

US Classification:

365242

Abstract:

An alpha particle resistant memory cell and array with complementary, differential data in, data out and write enable inputs capable of independent, simultaneous read/write operations. During write operations, clocked differential write and data inputs steer cell current to induce differential cell voltages indicative of the stored data. During read operations, a read select input shifts the voltage levels of the selected cell to produce a distinguishable output which dominates over the other cells to appropriately steer current at a sense amplifier to identify the binary cell contents. A 64 row by 12 bit register stack, with split word write, master reset and read enable is also disclosed.