David Carlton Whitworth

US Patent:

6651146, Nov 18, 2003

Filed:

Feb 24, 2000

Appl. No.:

09/513810

Inventors:

Mysore Sathyanarayana Srinivas - Austin TX
James William Vanfleet - Austin TX
David Blair Whitworth - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1200

US Classification:

711150, 707100, 707 8, 711168

Abstract:

The present invention discloses a method of managing lists in a multiprocessor system without the use of locks that prevent contention for the list. List management in a linear list with a front and a back of the list has applications where it is desirable to manage the list in a Last In First Out (LIFO) and a First In First Out (FIFO) or a combination of LIFO and FIFO. LIFO and FIFO list management can be done by restrictively adding data elements to the front, back and removing data elements from the front of a managed list. At certain times there can be contention for a list and either locking routines are in place to prevent contention or some other method is used to guarantee data element integrity. The present invention discloses a set of operations that when used with certain protocols allow two or more processors to access a list as a LIFO or FIFO in a multiprocessor system without the use of locks.

US Patent:

7640400, Dec 29, 2009

Filed:

Apr 10, 2007

Appl. No.:

11/733352

Inventors:

William A. Maron - Austin TX, US
Greg R. Mewhinney - Austin TX, US
Mysore S. Srinivas - Austin TX, US
David B. Whitworth - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711137, 711204, 711213

Abstract:

A method, computer program product, and system are provided for prefetching data into a cache memory. As a program is executed an object identifier is obtained of a first object of the program. A lookup operation is performed on a data structure to determine if the object identifier is present in the data structure. Responsive to the object identifier being present in the data structure, a referenced object identifier is retrieved that is referenced by the object identifier. Then, the data associated with the referenced object identifier is prefetched from main memory into the cache memory.

US Patent:

8230238, Jul 24, 2012

Filed:

Aug 25, 2008

Appl. No.:

12/197314

Inventors:

Miriam Allalouf - Mevaseret-Zion, IL
Michael E. Factor - Haifa, IL
Ronen Itshak Kat - Kfar-Saba, IL
Lee Charles LaFrese - Tucson AZ, US
Dalit Naor - Tel-Aviv, IL
David Blair Whitworth - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1/26
G06F 11/30

US Classification:

713300, 713310, 713320, 713321, 713322, 713323, 713324, 713330, 713340, 703 13, 711100

Abstract:

A method for determining power consumption in a data storage system is provided. The method comprises determining data access patterns for at least a first storage device in a storage system based on operations performed by the first storage device; and calculating power consumption for the storage system by interpolating costs associated with the operations performed by the first storage device, wherein the cost associated with each operation is determined based on: (1) various levels of activities for the first storage device and a mix of workload characteristics, and (2) predetermined power consumption measurements obtained from one or more benchmarks for same operations performed by a second storage device in a test environment.

US Patent:

8453122, May 28, 2013

Filed:

Nov 10, 2009

Appl. No.:

12/616005

Inventors:

Diane Garza Flemming - Pflugerville TX, US
Eric Philip Fried - Austin TX, US
Greg R. Mewhinney - Austin TX, US
David Blair Whitworth - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/44

US Classification:

717128

Abstract:

A symmetric multi-processor SMP system includes an SMP processor and operating system OS software that performs automatic SMP lock tracing analysis on an executing application program. System administrators, users or other entities initiate an automatic SMP lock tracing analysis. A particular thread of the executing application program requests and obtains a lock for a memory address pointer. A subsequent thread requests the same memory address pointer lock prior to the particular thread release of that lock. The subsequent thread begins to spin waiting for the release of that address pointer lock. When the subsequent thread reaches a predetermined maximum amount of wait time, MAXSPIN, a lock testing tool in the kernel of the OS detects the MAXSPIN condition. The OS performs a test to determine if the subsequent thread and address pointer lock meet the list of criteria set during initiation of the automatic lock trace method. The OS initiates an SMP lock trace capture automatically if all criteria or the arguments of the lock trace method are met.

US Patent:

8539281, Sep 17, 2013

Filed:

Apr 19, 2012

Appl. No.:

13/451266

Inventors:

Diane G. Flemming - Pflugerville TX, US
William A. Maron - Austin TX, US
Mysore S. Srinivas - Austin TX, US
David B. Whitworth - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 11/00

US Classification:

714 19, 714 18

Abstract:

According to one aspect of the present disclosure, a method and technique for managing rollback in a transactional memory environment is disclosed. The method includes, responsive to detecting a begin transaction directive by a processor supporting transactional memory processing, detecting an access of a first memory location not needing rollback and indicating that the first memory location does not need to be rolled back while detecting an access to a second memory location and indicating that a rollback will be required. The method also includes, responsive to detecting an end transaction directive after the begin transaction directive and a conflict requiring a rollback, omitting a rollback of the first memory location while performing rollback on the second memory location.

US Patent:

8539453, Sep 17, 2013

Filed:

Jun 30, 2010

Appl. No.:

12/827662

Inventors:

Diane G. Flemming - Pflugerville TX, US
Greg R. Mewhinney - Austin TX, US
Brian C. Twichell - Austin TX, US
David B. Whitworth - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/44
G06F 3/00

US Classification:

717128, 717158, 710 15

Abstract:

In an embodiment, a kernel performs autonomic input/output tracing and performance tuning. A first table is provided in a device driver framework and a second table in a kernel of a computer. An input/output device monitoring tool is provided in the device driver framework. A plurality of instructions in the kernel compares each value in the first table with each value in the second table. Responsive to a match of a value in the first table and a value in the second table, the kernel automatically runs a command line to perform a system trace, a component trace, or a tuning task. The first table is populated with a plurality of values calculated from a plurality of data in a plurality of device memories and in the controller memory and the second table is populated in accordance with a second plurality of inputs to the command line interface.

US Patent:

8549354, Oct 1, 2013

Filed:

May 23, 2011

Appl. No.:

13/113663

Inventors:

Diane G. Flemming - Pflugerville TX, US
William A. Maron - Austin TX, US
Mysore S. Srinivas - Austin TX, US
David B. Whitworth - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 11/00

US Classification:

714 19, 714 18

Abstract:

A system and technique for managing rollback in a transactional memory environment is disclosed. The system includes a processor, a transactional memory, and a transactional memory manager (TMM) configured to perform a rollback on the transactional memory. The TMM is configured to, responsive to detecting a begin transaction directive by the processor, detect an access of a first memory location of the transactional memory not needing rollback and indicate that the first memory location does not need to be rolled back while detecting an access to a second memory location of the transactional memory and indicating that a rollback will be required. The TMM is also configured to, responsive to detecting an end transaction directive after the begin transaction directive and a conflict requiring a rollback, omit a rollback of the first memory location while performing rollback on the second memory location.

US Patent:

8578388, Nov 5, 2013

Filed:

Oct 25, 2010

Appl. No.:

12/911102

Inventors:

Diane Flemming - Austin TX, US
Greg R. Mewhinney - Austin TX, US
David B. Whitworth - Austin TX, US
Randal C. Swanberg - Austin TX, US
Eric P. Fried - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/455
G06F 9/46

US Classification:

718105, 718 1, 718100, 718101, 718102

Abstract:

A hybrid CPU system wherein the plurality of processors forming the hybrid system are initially undifferentiated by type or class. Responsive to the sampling of the threads of a received and loaded computer application to be executed, the function of at least one of the processors is changed so that the threads of the sampled application may be most effectively processed/run on the hybrid system.