David None Zimmerman

US Patent:

7177211, Feb 13, 2007

Filed:

Nov 13, 2003

Appl. No.:

10/713673

Inventors:

David Zimmerman - El Dorado Hills CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 7/00

US Classification:

365201, 36518905

Abstract:

Method and apparatus for use with buffered memory modules are included among the embodiments. In exemplary systems, the memory module has a host-side memory channel port and a downstream memory channel port, allowing multiple modules to be chained point-to-point. In the present disclosure, a separate bus, such as a low-speed system management bus, connects to a memory module buffer. In response to commands received over the system management bus, the memory module can initiate commands and transmit those commands over its downstream memory channel port as if the commands originated from a host connected to the host-side memory channel port. This functionality allows module-to-module memory channels and memory modules to be tested independent of a host memory controller and host memory channel. Other embodiments are described and claimed.

US Patent:

7321997, Jan 22, 2008

Filed:

Mar 30, 2004

Appl. No.:

10/815217

Inventors:

David Zimmerman - El Dorado Hills CA, US
Edward Weaver - Sunnyvale CA, US
Ramasubramanian Rajamani - Cupertino CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 29/00
G01R 31/28

US Classification:

714718, 714724

Abstract:

A buffer logic within a memory module having the capability to carry out a test of another memory module to which it is coupled via a point-to-point bus through autonomously storing and transmitting a test pattern across that point-to-point bus to the other memory module, while further employing another buffer logic that is interposed between the two memory modules to pass on the test pattern, but intercept a signal received from the other memory module during the test and pass on an indication of the receipt of that signal to an analysis device to monitor the test.

US Patent:

7519891, Apr 14, 2009

Filed:

Sep 28, 2005

Appl. No.:

11/238897

Inventors:

David J. Zimmerman - El Dorado Hills CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G01R 31/28

US Classification:

714738

Abstract:

A memory includes a data generator to generate a data pattern, a transmitter in communication with the data generator, the transmitter to transmit the data pattern as a test data pattern, receiver to receive the test data pattern from the transmitter, and a comparator coupled with the receiver, the comparator to compare the data pattern with the test data pattern from the receiver and to verify proper operation of a memory channel. A method includes providing a seed value to a transmit and a receive pattern generator in a memory, generating data at the transmit pattern generator from the seed value and transmitting the data from the memory, looping the data to a receiver on the memory, using the seed value to generate data with the receive pattern generator, and comparing the data from the receive pattern generator and the transmit pattern generator to determine if any errors occurred.

US Patent:

7533204, May 12, 2009

Filed:

Dec 28, 2006

Appl. No.:

11/648482

Inventors:

David Zimmerman - El Dorado Hills CA, US
Jun Shi - San Jose CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/00

US Classification:

710104, 710 10, 711170, 36523003

Abstract:

According to one embodiment, a method is disclosed. The method includes receiving a bit pattern value at a first memory device from a host device via an interface to establish a first sideband address and the first memory device receiving a unique device identification (ID) from the host device.

US Patent:

7536267, May 19, 2009

Filed:

Nov 28, 2005

Appl. No.:

11/289186

Inventors:

David Zimmerman - El Dorado Hills CA, US
Jay J. Nejedlo - Wilsonville OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G01R 31/00

US Classification:

702117

Abstract:

In some embodiments, built-in self-test logic is provided for an integrated circuit (IC) device having memory controller logic to generate address and command information for accessing a memory device. Driver circuits are on-chip with the memory controller logic. The driver circuits have outputs that are coupled to on-chip signal pads, respectively. The BIST logic is coupled between the driver circuits and the controller logic. The BIST logic is to transmit, at speed, address and command information that has been generated by the controller logic using the driver circuits in a normal mode of operation for the device. In addition, the BIST logic is able to transmit, at speed, test symbols using the driver circuits in a test mode of operation for the IC device, during which a chip-to-chip connection between the IC device and another device is tested. Other embodiments are also described and claimed.

US Patent:

7580465, Aug 25, 2009

Filed:

Jun 30, 2005

Appl. No.:

11/174424

Inventors:

David J. Zimmerman - El Dorado Hills CA, US
Michael W. Williams - Citrus Heights CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04B 3/00
H04L 25/00

US Classification:

375257, 375219, 375220, 375222, 702117, 711167

Abstract:

Embodiments provide access to a memory over a high speed serial link at slower speeds than the high speed serial links regular operation. An embodiment may comprise a memory apparatus with a differential receiver coupled to a protocol recognition circuit, a low speed receiving circuit that has a first receiver coupled with a first input of the differential receiver and a second receiver coupled with a second input of the differential receiver, wherein the low speed receiving circuit is coupled with the protocol recognition circuit, allowing the first and second receivers to access the protocol recognition block at a different frequency than the differential receiver.

US Patent:

7644250, Jan 5, 2010

Filed:

Jun 30, 2006

Appl. No.:

11/480137

Inventors:

David J. Zimmerman - El Dorado Hills CA, US
Jun Shi - San Jose CA, US
Aaron Martin - El Dorado Hills CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/00

US Classification:

711170, 711100, 711115, 711171, 365 51, 365 63, 36518902, 36518903, 361600, 361728, 361679, 361683, 361684, 361731, 361733, 361736, 361737, 361748, 361755, 361760, 361763, 361754, 439 95, 439101, 439679, 439639, 439946

Abstract:

An orientation detector within a device package is used to establish the device orientation. A host controller coupled to the device supplies a control signal to at least one of the pins on the device during a setup phase. The pin that receives the control signal is used for active signaling during normal operations of the device. Based on the control signal, the orientation detector generates an orientation signal within the device. An analog or digital selector circuit connects the pins to correct internal circuit components according to the device orientation.

US Patent:

8607089, Dec 10, 2013

Filed:

May 19, 2011

Appl. No.:

13/111839

Inventors:

Shekoufeh Qawami - El Dorado Hills CA, US
Rajesh Sundaram - Folsom CA, US
David J. Zimmerman - El Dorado Hills CA, US
Robert W. Faber - Hillsboro OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1/12
G06F 13/42
H04L 5/00
H04L 7/00

US Classification:

713400, 713500, 711100, 711105, 711167, 710 22, 710 25, 710 61

Abstract:

A nonvolatile storage or memory device is accessed over a memory bus. The memory bus has an electrical interface typically used for volatile memory devices. A controller coupled to the bus sends synchronous data access commands to the nonvolatile memory device, and reads the response from the device bus based on an expected timing of a reply from the nonvolatile memory device. The controller determines the expected timing based on when the command was sent, and characteristics of the nonvolatile memory device. The controller may not need all the electrical signal lines available on the memory bus, and could issue data access commands to different groups of nonvolatile memory devices over different groups of electrical signal lines. The memory bus may be available and configured for either use with a memory controller and volatile memory devices, or a storage controller and nonvolatile memory devices.