Dean Liu from 850 Campus Dr, Daly City, CA 94015, Phone: 6509922123

Method For Reducing Supply Noise Near An On-Die Thermal Sensor
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US Patent:

6476663, Nov 5, 2002
Filed:

Aug 14, 2001
Appl. No.:

09/929151
Inventors:

Claude R. Gauthier - Fremont CA
Brian W. Amick - Austin TX
Tyler J. Thorp - Sunnyvale CA
Dean Liu - Sunnyvale CA
Pradeep R. Trivedi - Sunnyvale CA
Assignee:

Sun Microsystems, Inc. - Santa Clara CA
International Classification:

H01L 3500
US Classification:

327513, 327552
Abstract:

A method for reducing power supply noise in the power supply system of a thermal sensor has been developed. The method includes powering up a thermal sensor and inserting a shunting resistance across the power supply terminals. The shunting resistance is inserted in parallel with the thermal sensor.

Method For Reducing Peak To Peak Jitter In A Dual-Loop Delay Locked Loop
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US Patent:

6501328, Dec 31, 2002
Filed:

Aug 14, 2001
Appl. No.:

09/930435
Inventors:

Claude R. Gauthier - Fremont CA
Brian W. Amick - Austin TX
Tyler J. Thorp - Sunnyvale CA
Dean Liu - Sunnyvale CA
Pradeep R. Trivedi - Sunnyvale CA
Assignee:

Sun Microsystems, Inc. - CA
International Classification:

H03B 100
US Classification:

327551
Abstract:

A method for reducing power supply noise in the power supply system of a delay locked loop has been developed. The method includes powering up a delay locked loop and inserting a shunting resistance across the power supply terminals. The shunting resistance is inserted in parallel with the delay locked loop.

Reducing Pecl Voltage Variation
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US Patent:

6556041, Apr 29, 2003
Filed:

Oct 16, 2001
Appl. No.:

09/978869
Inventors:

Claude R. Gauthier - Fremont CA
Pradeep R. Trivedi - Sunnyvale CA
Dean Liu - Sunnyvale CA
Brian Amick - Sunnyvale CA
Assignee:

Sun Microsystems, Inc. - Santa Clara CA
International Classification:

H03K 1716
US Classification:

326 33, 326 73, 326 74, 326 27
Abstract:

A method for reducing voltage variation in a PECL based component has been developed. The method includes powering up a PECL based component, such as a receiver circuit for a PLL, and activating or inserting a shunting resistance across the power supply terminals of a PECL power supply. The shunting resistance is inserted in parallel with the PECL based component, and is controllable such that the resistance can be selectively switched âonâ and/or âoff. â.

Programmable Leakage Current Offset For Delay Locked Loop
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US Patent:

6573770, Jun 3, 2003
Filed:

Aug 29, 2002
Appl. No.:

10/230726
Inventors:

Claude R. Gauthier - Fremont CA
Pradeep R. Trivedi - Sunnyvale CA
Brian W. Amick - Austin TX
Dean Liu - Sunnyvale CA
Assignee:

Sun Microsystems, Inc. - Santa Clara CA
International Classification:

H03L 706
US Classification:

327156, 327157
Abstract:

A method and apparatus for post-fabrication adjustment of a delay locked loop leakage current is provided. The adjustment system includes an adjustment circuit that adjusts a leakage current offset circuit to compensate for the leakage current of a capacitor in the delay locked loop. The capacitor connects to a control voltage of the delay locked loop. Such control of the leakage current in the delay locked loop allows a designer to achieve a desired delay locked loop operating characteristic after the delay locked loop has been fabricated.

Post-Silicon Bias-Generator Control For A Differential Phase Locked Loop
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US Patent:

6593784, Jul 15, 2003
Filed:

Apr 24, 2002
Appl. No.:

10/131299
Inventors:

Claude Gauthier - Fremont CA
Brian Amick - Austin TX
Pradeep Trivedi - Sunnyvale CA
Dean Liu - Sunnyvale CA
Assignee:

Sun Microsystems, Inc. - Santa Clara CA
International Classification:

H03L 706
US Classification:

327156, 327159, 331 34, 331 40
Abstract:

A technique for adjusting a bias-generator in a phase locked loop after fabrication of the phase locked loop is provided. The technique involves use of an adjustment circuit operatively connected to the bias-generator, where the adjustment circuit is controllable to facilitate a modification of a voltage output by the bias-generator. Such control of the voltage output by the bias-generator allows a designer to achieve a desired phase locked loop performance characteristic after the phase locked loop has been fabricated.

Programmable Bias-Generator For Self-Biasing A Delay Locked Loop
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US Patent:

6597218, Jul 22, 2003
Filed:

Apr 24, 2002
Appl. No.:

10/131308
Inventors:

Claude Gauthier - Fremont CA
Brian Amick - Austin TX
Dean Liu - Sunnyvale CA
Pradeep Trivedi - Sunnyvale CA
Assignee:

Sun Microsystems, Inc. - Santa Clara CA
International Classification:

H03L 706
US Classification:

327158, 327161, 327272, 331DIG 2, 375376
Abstract:

A technique Readjusting a bias-generator in a delay locked loop after fabrication of the delay locked loop. The technique involves use of an adjustment circuit operatively connected to the bias-generator, where the adjustment circuit is controllable to facilitate a modification of a voltage output by the bias-generator. Such control of the voltage output by the bias-generator allows a designer to achieve a desired delay locked loop performance characteristic after the delay locked loop has been fabricated.

Calibration Technique For Delay Locked Loop Leakage Current
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US Patent:

6614287, Sep 2, 2003
Filed:

Aug 13, 2002
Appl. No.:

10/217926
Inventors:

Claude R. Gauthier - Fremont CA
Pradeep Trivedi - Sunnyvale CA
Brian W. Amick - Austin TX
Dean Liu - Sunnyvale CA
Assignee:

Sun Microsystems, Inc. - Santa Clara CA
International Classification:

H03K 2100
US Classification:

327362, 327157
Abstract:

A method and apparatus for post-fabrication calibration and adjustment of a delay locked loop leakage current is provided. The calibration and adjustment system includes an adjustment circuit that adjusts a leakage current offset circuit to compensate for the leakage current of a capacitor. The capacitor connects to a control voltage of the delay locked loop. Such control of the leakage current in the delay locked loop allows a designer to achieve a desired delay locked loop operating characteristic after the delay locked loop has been fabricated. A representative value of the amount of adjustment desired in the leakage current may be stored and subsequently read to adjust the delay locked loop.

Apparatus For Reducing The Supply Noise Near Large Clock Drivers
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US Patent:

6618277, Sep 9, 2003
Filed:

Aug 14, 2001
Appl. No.:

09/930537
Inventors:

Claude R. Gauthier - Fremont CA
Brian W. Amick - Austin TX
Tyler J. Thorp - Sunnyvale CA
Pradeep R. Trivedi - Sunnyvale CA
Dean Liu - Sunnyvale CA
Assignee:

Sun Microsystems, Inc. - Santa Clara CA
International Classification:

H02M 700
US Classification:

363 74, 327540
Abstract:

An apparatus for reducing power supply noise in the power supply system of a clock driver has been developed. The apparatus includes a clock driver with a power supply system connected to the clock driver and a shunting resistor connected across the power supply system in parallel with the clock driver.