Debra L Harris

US Patent:

6346427, Feb 12, 2002

Filed:

Aug 18, 1999

Appl. No.:

09/376246

Inventors:

Harry N. Gardner - Colorado Springs CO
Debra S. Harris - Colorado Springs CO
Michael D. Lahey - Colorado Springs CO
Stacia L. Patton - Colorado Springs CO
Peter M. Pohlenz - Colorado Springs CO

Assignee:

UTMC Microelectronic Systems Inc. - Colorado Springs CO

International Classification:

H01L 2100

US Classification:

438 10

Abstract:

A method of manufacturing an integrated circuit including adjusting a parameter of the operation of the integrated circuit, such as power dissipation, after prototype testing by changing only one mask. If prototype testing indicates that the performance specification for power dissipation, for example, is not met, the power dissipation can be adjusted by changing the size of the active areas to change the channel width of the gates of the circuit, by changing the size of the patterns of the active area masks. To decrease power dissipation, the size of the active area is decreased. Only the active mask need be changed. Preferably, the active area around the original contacts are maintained so that the positions of the contacts need not be changed. Consequently, the mask for defining the position of the contacts and the masks for defining the metallization layers need not be changed. To increase power dissipation, the size of the active areas is increased.

US Patent:

6453447, Sep 17, 2002

Filed:

Aug 16, 2000

Appl. No.:

09/640344

Inventors:

Harry N. Gardner - Colorado Springs CO
Debra S. Harris - Colorado Springs CO
Michael D. Lahey - Colorado Springs CO
Stacia L. Patton - Colorado Springs CO
Peter M. Pohlenz - Colorado Springs CO

Assignee:

Aeroflex UTMC Microelectronic Systems Inc. - Colorado Springs CO

International Classification:

G06F 1750

US Classification:

716 3, 715 2, 715 17

Abstract:

Functional and geometrical sub-components of logic circuits are defined and used in the design of integrated circuits to facilitate the transformation of an integrated circuit design for fabrication at foundries with different design rules.

US Patent:

58703322, Feb 9, 1999

Filed:

Apr 22, 1996

Appl. No.:

8/635794

Inventors:

Michael D. Lahey - Colorado Springs CO
Debra S. Harris - Colorado Springs CO
Harry N. Gardner - Colorado Springs CO
Michael J. Barry - Tigard OR

Assignee:

United Technologies Corporation - Hartford CT

International Classification:

G11C 1140

US Classification:

365156

Abstract:

A high reliability logic circuit designed to withstand a single event upset (SEU) induced by an ion transitioning through a semiconductor structure is embodied in a memory circuit which includes a first memory cell and a second memory cell. The first and second memory cells receive a first input signal and a second input signal. The memory cells contain a logic circuit for producing a logic signal output driven by either a pullup or pulldown driver when the first and second input signals are of a desired logic state and produces a high impedance output if either input signal is not of their respective desired logic states. The memory cells also have sufficient nodal capacitance such that the output from the first or second memory cell will not be corrupted by an SEU in the logic circuit of either the first or second memory cell. The outputs of the first memory cell and second memory cell are further summed in analog fashion to produce a single output from the memory circuit. The summing of the output signals from the first and second memory cell prevents a single error in either memory cell from propagating to a next stage.