Deepak K Singh

US Patent:

20200249954, Aug 6, 2020

Filed:

Feb 1, 2019

Appl. No.:

16/264795

Inventors:

- Armonk NY, US
Joshua W. Bowman - Austin TX, US
Christopher M. Mueller - Round Rock TX, US
Dung Q. Nguyen - Austin TX, US
Deepak K. Singh - Apex NC, US
Brian W. Thompto - Austin TX, US

International Classification:

G06F 9/38

Abstract:

An approach is disclosed that in one or more embodiments includes receiving an indicator to issue an out-of-order instruction or a type of out-of-order instruction in-order; receiving a first instruction; determining whether the first instruction corresponds to the indicated out-of-order instruction or the type of out-of-order instruction; writing, in response to determining that the first instruction corresponds to the indicated out-of-order instruction or the type of out-of-order instruction, an instruction identifier and a dependent instruction opcode into a first queue and an issue queue of the processor; receiving at least one subsequent instruction; determining whether an instruction opcode of the subsequent instructions matches the dependent instruction opcode of the first instruction; and writing, in response to determining the instruction opcode of the subsequent instruction matches the dependent instruction opcode of the instruction, a dependent instruction identifier for the subsequent instruction into the issue queue.

US Patent:

20200065110, Feb 27, 2020

Filed:

Aug 23, 2018

Appl. No.:

16/110178

Inventors:

- Armonk NY, US
Dung Q. NGUYEN - Austin TX, US
Susan E. EISEN - Round Rock TX, US
Christopher M. MUELLER - Round Rock TX, US
Joe LEE - Round Rock TX, US
Deepak K. SINGH - Apex NC, US

International Classification:

G06F 9/38

Abstract:

Method and apparatus for stopping completions using stop codes in an instruction completion table are provided by during a first clock cycle, in response to determining that a given entry in an Instruction Completion Table (ICT) is finalized and is associated with a stop code, completing, according to a program order, instructions included in one or more finalized entries of the ICT located in the ICT before the given entry; during a second clock cycle, after completing the instructions, performing exception processing for a special instruction included in the given entry; and during a third clock cycle, after processing the special instruction, completing, according to the program order, additional instructions in one or more finalized entries located in the ICT after the given entry.