Deepak K Singh

US Patent:

20020097069, Jul 25, 2002

Filed:

Jan 25, 2001

Appl. No.:

09/769075

Inventors:

Santanu Dutta - Sunnyvale CA, US
Deepak Singh - Santa Clara CA, US

International Classification:

H03K019/00

US Classification:

326/093000

Abstract:

The precharge of a domino logic stage is controlled based on the precharge delay of a prior domino logic stage. The precharge of the logic stage does not occur until the output of the prior logic stage corresponds to the precharge logic state. Because the precharge logic state output of a preceding stage is an inactive state of a subsequent logic stage, the logic function of the subsequent logic stage is in a non-conducting state when the output of the prior logic stage is in the precharge logic state. By providing the precharge to a subsequent stage only after the output of the prior stage is in the precharge state, there can be no DC current flow during the precharge of the subsequent stage, and the need for an evaluation transistor to block the DC current flow during precharge is eliminated. The elimination of the evaluation transistor eliminates the delay introduced by the evaluation transistor in a precharge logic stage, reduces the circuit area for the logic stage, reduces the load on the clock circuit, and reduces the power consumption of each logic stage.

US Patent:

20030088602, May 8, 2003

Filed:

Nov 8, 2001

Appl. No.:

10/005551

Inventors:

Santanu Dutta - Sunnyvale CA, US
Deepak Singh - Santa Clara CA, US

Assignee:

Koninklijke Philips Electronics N.V.

International Classification:

G06F007/50

US Classification:

708/700000

Abstract:

An arithmetic computation circuit is implemented to significantly increase throughput and thereby permit processing of relatively large binary numbers in a relatively small period of time. In one embodiment, the arithmetic computation circuit adapted to add a first binary operand of N bits and a second binary operand of M bits, where N is greater than or equal to M. The circuit includes an adder and a multiplexer circuit. The adder is adapted to combine representative sets of least-significant bits of the first and second binary operands together to produce a least-significant bits partial sum and a carryout. The multiplexer circuit is adapted to output a most-significant bits partial sum by passing one of: a representative set of most-significant bits of the first binary operand, and an offset of the representative set of most-significant bits of the first binary operand; the selection of these inputs is responsive to selection data that is a function of the most-significant bit of the representative set of least-significant bits of the first binary operand.

Address:

4548 Wheeler Dr, Fremont, CA 94538

VIN:

5FNYF18747B018800

Make:

HONDA

Model:

PILOT

Year:

2007