Deepak Singh

US Patent:

20200249954, Aug 6, 2020

Filed:

Feb 1, 2019

Appl. No.:

16/264795

Inventors:

- Armonk NY, US
Joshua W. Bowman - Austin TX, US
Christopher M. Mueller - Round Rock TX, US
Dung Q. Nguyen - Austin TX, US
Deepak K. Singh - Apex NC, US
Brian W. Thompto - Austin TX, US

International Classification:

G06F 9/38

Abstract:

An approach is disclosed that in one or more embodiments includes receiving an indicator to issue an out-of-order instruction or a type of out-of-order instruction in-order; receiving a first instruction; determining whether the first instruction corresponds to the indicated out-of-order instruction or the type of out-of-order instruction; writing, in response to determining that the first instruction corresponds to the indicated out-of-order instruction or the type of out-of-order instruction, an instruction identifier and a dependent instruction opcode into a first queue and an issue queue of the processor; receiving at least one subsequent instruction; determining whether an instruction opcode of the subsequent instructions matches the dependent instruction opcode of the first instruction; and writing, in response to determining the instruction opcode of the subsequent instruction matches the dependent instruction opcode of the instruction, a dependent instruction identifier for the subsequent instruction into the issue queue.

US Patent:

20200241880, Jul 30, 2020

Filed:

Apr 17, 2020

Appl. No.:

16/851377

Inventors:

- Armonk NY, US
Susan E. EISEN - Round Rock TX, US
Dung Q. NGUYEN - Austin TX, US
Glenn O. KINCAID - Austin TX, US
Joe LEE - Round Rock TX, US
Deepak K. SINGH - Apex NC, US

International Classification:

G06F 9/38
G06F 9/34

Abstract:

Method and apparatus for a completion mechanism for a microprocessor are provided by identifying entries in a section of an Instruction Completion Table (ICT) that are marked as ready to complete via corresponding Ready to Complete (RTC) status bits; determining a tail pointer indicating a start of the entries in the ICT that are ready for completion; determining a head pointer that indicates an end of the entries in the ICT that are ready for completion; completing instructions included in the entries between the tail pointer and the head pointer; and updating the tail pointer to a value of the head pointer for a subsequent instruction completion round.

US Patent:

20200142697, May 7, 2020

Filed:

Nov 7, 2018

Appl. No.:

16/182760

Inventors:

- Armonk NY, US
Susan E. Eisen - Round Rock TX, US
Glenn O. Kincaid - Austin TX, US
Dung Q. Nguyen - Austin TX, US
Deepak K. Singh - Raleigh NC, US
Gaurav Mittal - Round Rock TX, US
Christopher M. Mueller - Round Rock TX, US

International Classification:

G06F 9/30
G06F 9/38

Abstract:

A computer-implemented method, computer program product, and computer processing system are provided. The method includes processing, by a superscalar processing pipeline, respective sets of instructions in respective instruction processing cycles using an Instruction Completion Table (ICT) with a Ready-To-Complete (RTC) vector. The ICT includes a plurality of entries, each corresponding to a respective one of the instructions. A Next-To-Complete (NTC) instruction from among the respective sets of instructions is computed using the RTC vector.

US Patent:

20200065102, Feb 27, 2020

Filed:

Aug 23, 2018

Appl. No.:

16/109952

Inventors:

- Armonk NY, US
Susan E. EISEN - Round Rock TX, US
Dung Q. NGUYEN - Austin TX, US
Glenn O. KINCAID - Austin TX, US
Joe LEE - Round Rock TX, US
Deepak K. SINGH - Apex NC, US

International Classification:

G06F 9/34
G06F 9/38
G06F 9/30

Abstract:

Method and apparatus for a completion mechanism for a microprocessor are provided by marking entries in a section of an Instruction Completion Table (ICT) as ready to complete using corresponding Ready to Complete (RTC) status bits; determining a tail pointer indicating a start of the entries in the ICT that are ready for completion in a current clock cycle; performing a counting leading ones on an RTC vector that organizes the RTC status bits according to a program order for completing the entries to determine a count leading ones pointer that indicates an end of the entries in the ICT that are ready for completion in the current clock cycle; completing instructions included in the entries between the tail pointer and the count leading ones pointer in one clock cycle; and updating the tail pointer to a value of the count leading ones pointer for a subsequent clock cycle.

US Patent:

20200065103, Feb 27, 2020

Filed:

Aug 23, 2018

Appl. No.:

16/110061

Inventors:

- Armonk NY, US
Susan E. EISEN - Round Rock TX, US
Dung Q. NGUYEN - Austin TX, US
Glenn O. KINCAID - Austin TX, US
Joe LEE - Round Rock TX, US
Deepak K. SINGH - Apex NC, US

International Classification:

G06F 9/34
G06F 9/38
G06F 9/30

Abstract:

Method and apparatus for completing atomic instructions in a microprocessor may be provided by identifying from a program-ordered Instruction Completion Table (ICT) a last entry in a completion window of instructions for completion in a current clock cycle of a processor; in response to determining that the last entry includes an atomic instruction that straddles the completion window: excluding the last entry from completion during the current clock cycle; completing instructions in the completion window for the current clock cycle; and shifting the completion window to include the last entry and a next entry adjacent to the last entry in the ICT in a next clock cycle.

US Patent:

20200065110, Feb 27, 2020

Filed:

Aug 23, 2018

Appl. No.:

16/110178

Inventors:

- Armonk NY, US
Dung Q. NGUYEN - Austin TX, US
Susan E. EISEN - Round Rock TX, US
Christopher M. MUELLER - Round Rock TX, US
Joe LEE - Round Rock TX, US
Deepak K. SINGH - Apex NC, US

International Classification:

G06F 9/38

Abstract:

Method and apparatus for stopping completions using stop codes in an instruction completion table are provided by during a first clock cycle, in response to determining that a given entry in an Instruction Completion Table (ICT) is finalized and is associated with a stop code, completing, according to a program order, instructions included in one or more finalized entries of the ICT located in the ICT before the given entry; during a second clock cycle, after completing the instructions, performing exception processing for a special instruction included in the given entry; and during a third clock cycle, after processing the special instruction, completing, according to the program order, additional instructions in one or more finalized entries located in the ICT after the given entry.

US Patent:

20190187993, Jun 20, 2019

Filed:

Dec 18, 2017

Appl. No.:

15/845871

Inventors:

- Armonk NY, US
Susan E. EISEN - Round Rock TX, US
Dung Q. NGUYEN - Austin TX, US
Glenn O. KINCAID - Austin TX, US
Christopher M. MUELLER - Round Rock TX, US
Tu-An T. NGUYEN - Austin TX, US
Gaurav MITTAL - Round Rock TX, US
Deepak K. SINGH - Apex NC, US

International Classification:

G06F 9/38
G06F 9/30

Abstract:

A simultaneous multithreading processor and related method of operating are disclosed. The method comprises dispatching portions of a first instruction to be executed by a respective plurality of execution units of the processor; receiving, at an instruction completion table of the processor, respective finish reports responsive to execution of the portions of the first instruction; determining, using the received finish reports, that all of the portions of the first instruction have been executed; and updating the instruction completion table to indicate that the first instruction is ready for completion.