Duc Hong Ngo

US Patent:

58282548, Oct 27, 1998

Filed:

Jan 11, 1996

Appl. No.:

8/584925

Inventors:

Mehrdad Nayebi - Palo Alto CA
Duc Ngo - San Jose CA

Assignee:

Sony Corporation - Tokyo
Sony Electronics, Inc. - Park Ridge NJ

International Classification:

H03L 706

US Classification:

327157

Abstract:

An error regulator circuit for use within a charge pump circuit of a phase-locked loop monitors levels of the control signals used to control the charge pump circuit. When one of the control signals remains at a predetermined voltage level for a predetermined period of time, indicating that the charge pump circuit is in a hold mode or an inactive period of time, the current sources within the charge pump used to charge and discharge a charge pump capacitor are temporarily disabled. During a hold or inactive period when one of the control signals used to control the charge pump circuit remains at the predetermined voltage level for more than a predetermined period of time, the current sources of the charge pump circuit are disabled and the charge pump circuit is prevented from charging or discharging the charge pump capacitor until the current sources are re-enabled, thereby allowing the charge pump circuit to maintain an appropriate level of charge across the capacitor during an inactive or hold period. The current sources are re-enabled when the control signal which was at the predetermined voltage level for more than the predetermined period of time is no longer at the predetermined voltage level.

US Patent:

57195323, Feb 17, 1998

Filed:

Jan 11, 1996

Appl. No.:

8/584750

Inventors:

Mehrdad Nayebi - Palo Alto CA
Duc Ngo - San Jose CA

Assignee:

Sony Corporation - Tokyo
Sony Electronics Inc. - Park Ridge NJ

International Classification:

H03L 7095
H03L 700

US Classification:

331 20

Abstract:

A horizontal lock detector circuit monitors charge pump control signals within a horizontal phase-lock loop to determine when the sampling pulses generated by the video system are locked in phase with the synchronization pulses of the input composite video signal. An output signal is generated by the lock detector circuit which is active when the sampling pulses are locked in phase with the input signal and inactive when the sampling pulses are not locked in phase with the input signal. The charge pump control signals are generated by a phase detector circuit within the phase-lock loop in response to a difference in phase between the sampling pulses and the input signal. Once the sampling pulses are locked in phase with the input signal, the charge pump control signals will become inactive. A current source is enabled when either of the charge pump control signals are active. The current source builds up a first level of charge on a first capacitor during the horizontal blanking period.

US Patent:

56893094, Nov 18, 1997

Filed:

Jan 11, 1996

Appl. No.:

8/584924

Inventors:

Mehrdad Nayebi - Palo Alto CA
Duc Trong Ngo - San Jose CA
Steve Edwards - San Jose CA

Assignee:

Sony Corporation
Sony Electronics, Inc. - Park Ridge NJ

International Classification:

H04N 974

US Classification:

348584

Abstract:

A mixer control circuit generates content control signals which are used by a mixer circuit to control the content of an output signal. The output signal will include either an analog signal, a digital signal or a mixture of the analog and digital signals. The level of a digital content control signal corresponds to the percentage of the output signal which includes the digital signal. The level of an analog content control signal corresponds to the percentage of the output signal which includes the analog signal. When the output signal includes a mixture of the analog and digital signals, a differential pair and an external control voltage are used to specify the percentage of each signal to be included within the output signal. During a horizontal blanking period, when the signals are being mixed, the differential pair and the external control voltage are bypassed and only the analog signal is included within the output signal. When the output signal is to include only one of the signals, either analog or digital, the differential pair and the external control voltage are also bypassed.

US Patent:

59260637, Jul 20, 1999

Filed:

May 8, 1997

Appl. No.:

8/852919

Inventors:

Mehrdad Nayebi - Palo Alto CA
Duc Ngo - San Jose CA

Assignee:

Sony Corporation - Tokyo
Sony Electronics, Inc. - Park Ridge NJ

International Classification:

H03K 500
H03H 1104

US Classification:

327553

Abstract:

A method of and apparatus for selectively engaging an internal trap filter and implementing an external trap filter through a single pin routes a separate luminance signal through the pin or through an internal trap filter based on the logical voltage level at the pin. When implementing an external trap filter the external components comprising the filter are coupled between the pin and ground and a voltage level of the pin is maintained at a logical low voltage level. When the pin is at a logical low voltage level, two path switches are closed and the separate luminance signal is routed through the pin to be filtered by the external trap filter. The internal trap filter is engaged by coupling a precision resistor between the pin and a power supply voltage thereby pulling the voltage level of the pin to a logical high voltage level and opening the two path switches to bypass the pin and route the separate luminance signal through an internal trap filter. When the voltage level of the pin is at a logical high voltage level, a bias switch is closed thereby providing a bias current, created from the voltage drop across the precision resistor, to the internal trap filter. The internal trap filter is activated by the bias current and filters the separate luminance signal according to the value of the bias current, before the separate luminance signal is combined with the separate chrominance signal.

US Patent:

60438509, Mar 28, 2000

Filed:

May 8, 1997

Appl. No.:

8/852918

Inventors:

Mehrdad Nayebi - Palo Alto CA
Duc Ngo - San Jose CA

Assignee:

Sony Corporation - Tokyo
Sony Electronics, Inc. - Park Ridge NJ

International Classification:

H04N 945

US Classification:

348506

Abstract:

A burst gate pulse generator circuit generates a burst gate pulse signal representative of a time period during which a burst signal is present within a composite video signal without requiring external components. Each period of the composite video signal includes a horizontal synchronization signal pulse, a burst signal and a video information signal. A pair of integrated capacitors are discharged during the horizontal synchronization pulse. The capacitors are charged at different rates by two current sources after the horizontal synchronization pulse. A first amount of charge across a first capacitor rises above a predetermined threshold level in a first time period. The burst gate pulse signal is activated when the first amount of charge rises above the predetermined threshold level. This occurs before the burst signal is present within the composite video signal. A second amount of charge across a second capacitor rises above the predetermined threshold level in a second time period.

US Patent:

58122087, Sep 22, 1998

Filed:

Jan 11, 1996

Appl. No.:

8/585429

Inventors:

Mehrdad Nayebi - Palo Alto CA
Duc Ngo - San Jose CA

Assignee:

Sony Corporation - Tokyo
Sony Electronics, Inc. - Park Ridge NJ

International Classification:

H04N 945
H04N 9455

US Classification:

348506

Abstract:

A burst separator and slicer circuit separates the burst signal from an input composite video signal. Each period of the input composite video signal includes a horizontal synchronization signal, a burst signal and a video information signal. A burst gate pulse signal representing the presence of the burst signal within the input composite video signal is received by the burst separator and slicer circuit. During the burst period, when the burst gate pulse is active, the burst signal is extracted from the input composite video signal and converted to a square waveform. A differential pair and comparator circuit monitors the input composite video signal and compares it to a constant level reference voltage signal. A constant high voltage level is output when the burst signal is greater than the constant level reference signal. A constant low voltage level is output when the burst signal is less than the constant level reference signal.

US Patent:

60183705, Jan 25, 2000

Filed:

May 8, 1997

Appl. No.:

8/848387

Inventors:

Mehrdad Nayebi - Palo Alto CA
Duc Ngo - San Jose CA

Assignee:

Sony Corporation - Tokyo
Sony Electronics, Inc. - Park Ridge NJ

International Classification:

H04N 510
H04N 508

US Classification:

348525

Abstract:

A current source and threshold voltage generation circuit generates a current, through a ratio of devices, and a corresponding threshold voltage signal, to be utilized by a timing circuit for generating a timing ramp and determining when the timing ramp crosses the threshold voltage signal. The current is generated through a current generation circuit, using a ratio of matched devices. Preferably, the matched devices are transistors. The current is then utilized by a timing circuit to charge a charge storage device to a level above the level of the threshold voltage signal. The current is also mirrored, appropriately increased and used to generate the threshold voltage signal which is compared to the charge stored on the charge storage device. Accordingly, any errors in the generation of the current are also reflected in the level of the threshold voltage signal, thereby eliminating the potential for errors in the timing ramp signal generated by the timing circuit. Preferably, the charge storage device is a capacitor and the timing circuit is an HHK video circuit.

US Patent:

59992212, Dec 7, 1999

Filed:

May 8, 1997

Appl. No.:

8/848399

Inventors:

Mehrdad Nayebi - Palo Alto CA
Duc Ngo - San Jose CA

Assignee:

Sony Corporation - Tokyo
Sony Electronics, Inc. - Park Ridge NJ

International Classification:

H04N 506

US Classification:

348521

Abstract:

A horizontal synchronization pulse generation circuit generates a horizontal synchronization pulse to be added to an encoded composite video signal. An input receiving circuit receives an encoded input video signal representing video information received from input video signals. An output video signal represents the encoded input video signal in all portions of the signal except the horizontal synchronization period. During the horizontal synchronization period a current is switched through a path resistor and used to generate the voltage level of the horizontal synchronization pulse. The voltage drop across the path resistor during the horizontal synchronization period is applied directly to the output video signal thereby generating a horizontal synchronization pulse. The current switched through the path resistor is generated by a voltage drop across a current resistor. The ratio of the path resistor to the current resistor is matched, allowing the required signal accuracy to be achieved in the voltage drop across the path resistor and generating the appropriate voltage drop across the path resistor according to the current flowing through the current resistor.