Earnest B Wilson

US Patent:

59602708, Sep 28, 1999

Filed:

Aug 11, 1997

Appl. No.:

8/907990

Inventors:

Veena Misra - Austin TX
Suresh Venkatesan - Austin TX
Christopher C. Hobbs - Austin TX
Brad Smith - Austin TX
Jeffrey S. Cope - Austin TX
Earnest B. Wilson - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 21336

US Classification:

438197

Abstract:

A method for forming a metal gate MOS transistor begins by forming source and drain electrodes (26, 28, and/or 118) within a substrate (12 or 102). These source and drain regions (26, 28, and 118) are self-aligned to a lithographically-patterned feature (24 or 108). After formation of the source and drain regions, the features (24 and 108 are processed to fill these features with a metallic gate layer (28a or 128a). This metal layer (28a or 128a) is then chemically mechanically polished (CMPed) to form a metallic plug region (28b or 128b) within the features (24 or 108). The plug region (28b or 128b) is formed in either an inlaid or dual inlaid manner wherein this metallic plug region (28b or 128b) is self-aligned to the previously formed source and drain regions and preferably functions as a metal MOS gate region.