Eric M Nequist from 3054 Lakeshore Dr, Douglas, MI 49406, age 63, Phone: 2698575013

Shape Abstraction Mechanism
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US Patent:

6983440, Jan 3, 2006
Filed:

Jan 14, 2003
Appl. No.:

10/342824
Inventors:

Eric Nequist - Monte Sereno CA, US
Assignee:

Cadence Design Systems, Inc. - San Jose CA
International Classification:

G06F 17/50
US Classification:

716 11, 716 8, 716 9, 716 10
Abstract:

A method of simulating a design of an electronic system having multiple layers includes, for each layer, storing a plurality of shape occurrences for the layer. A hierarchy of shape instances having a plurality of levels is generated. Each shape instance corresponds to one of the shape occurrences. A hierarchy of shadow instances having a plurality of levels is generated.

Non-Orthogonal Structures And Space Tiles For Layout, Placement, And Routing Of An Integrated Circuit
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US Patent:

7096445, Aug 22, 2006
Filed:

Jan 14, 2003
Appl. No.:

10/342863
Inventors:

Steven Lee Pucci - Los Gatos CA, US
Eric Martin Nequist - Monte Sereno CA, US
Assignee:

Cadence Design Systems, Inc. - San Jose CA
International Classification:

G06F 17/50
US Classification:

716 8, 716 7, 716 12
Abstract:

Disclosed is an improved approach for maintaining the structures for objects in a layout. A single type of structure is maintained that can be used to store or track a polygon of any shape, as long as the shape possesses a supported number of sides. The structure is capable of supporting irregular polygons or objects having angled edges. In one approach, the structure maintains information about each polygon as if that polygon is an octagon. Therefore, any polygon having eight or less orthogonal or diagonal sides can be supported using this structure.

Zone Tree Method And Mechanism
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US Patent:

7100128, Aug 29, 2006
Filed:

Jan 14, 2003
Appl. No.:

10/342823
Inventors:

Eric Nequist - Monte Sereno CA, US
Jeffrey Scott Salowe - Cupertino CA, US
Steven Lee Pucci - Los Gatos CA, US
Assignee:

Cadence Design Systems, Inc. - San Jose CA
International Classification:

G06F 17/50
US Classification:

716 4, 716 7, 716 2
Abstract:

A method of analyzing a design of an electronic circuit uses slices. The method includes generating one or more slices, each slice comprising a contiguous region of the design, and generating an set comprising one or more bins for each slice. A search for an object may be performed by determining a search area, and identifying slices containing at least a portion of the search area. For each identified slice, each object within the search area is associated with one of the bins of the set for the slice.

Hierarchical Gcell Method And Mechanism
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US Patent:

7100129, Aug 29, 2006
Filed:

Jan 14, 2003
Appl. No.:

10/342862
Inventors:

Jeffrey Scott Salowe - Cupertino CA, US
Eric Nequist - Monte Sereno CA, US
Assignee:

Cadence Design Systems, Inc. - San Jose CA
International Classification:

G06F 17/50
US Classification:

716 4, 716 5, 716 8, 716 11, 716 12, 716 13
Abstract:

A method of analyzing a design of an electronic circuit includes tessellating the design into a grid of rectangles, selecting at least one rectangle as a first level parent rectangle, and generating a plurality of second level child rectangles based on the first level parent rectangle.

Method And Mechanism For Determining Shape Connectivity
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US Patent:

7461359, Dec 2, 2008
Filed:

Sep 15, 2005
Appl. No.:

11/229344
Inventors:

Eric Nequist - Monte Sereno CA, US
Assignee:

Cadence Design Systems, Inc. - San Jose CA
International Classification:

G06F 17/50
US Classification:

716 1, 716 3, 716 4, 716 5, 716 12, 716 18
Abstract:

A method and mechanism is disclosed for identifying connected shapes and objects in an electrical design. The entire hierarchical design does not have to be flattened to perform the operation of identifying connected objects for a specific object. Instead of unfolding the entire design hierarchy, only the specific instances of shapes falling within the geometric bounds of shapes need to be unfolded to perform the search.

Non-Orthogonal Structures And Space Tiles For Layout, Placement, And Routing Of An Integrated Circuit
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US Patent:

7516433, Apr 7, 2009
Filed:

Aug 21, 2006
Appl. No.:

11/507870
Inventors:

Steven Lee Pucci - Los Gatos CA, US
Eric Martin Nequist - Monte Sereno CA, US
Assignee:

Cadence Design Systems, Inc. - San Jose CA
International Classification:

G06F 17/50
US Classification:

716 7, 716 13, 716 14
Abstract:

Disclosed is an improved approach for maintaining the structures for objects in a layout. A single type of structure is maintained that can be used to store or track a polygon of any shape, as long as the shape possesses a supported number of sides. The structure is capable of supporting irregular polygons or objects having angled edges. In one approach, the structure maintains information about each polygon as if that polygon is an octagon. Therefore, any polygon having eight or less orthogonal or diagonal sides can be supported using this structure.

Method And System For Implementing Layout, Placement, And Routing With Merged Shapes
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US Patent:

7590955, Sep 15, 2009
Filed:

Dec 29, 2006
Appl. No.:

11/648151
Inventors:

Eric Nequist - Monte Sereno CA, US
Richard Brashears - San Jose CA, US
Assignee:

Cadence Design Systems, Inc. - San Jose CA
International Classification:

G06F 17/50
US Classification:

716 4, 716 1, 716 2, 716 11
Abstract:

Disclosed is an improved method, system, and computer program product for performing layout, placement, and routing for electronic designs. According to some approaches, multiple objects are considered as a collective object or shape, based upon the proximity of one or more of the objects to one or more other objects. The type and/or configuration of the collective object is based, for example, upon the type of rule that is being considered for the layout, placement, or routing operation.

Representation, Configuration, And Reconfiguration Of Routing Method And System
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US Patent:

7614028, Nov 3, 2009
Filed:

Apr 27, 2007
Appl. No.:

11/741668
Inventors:

Eric Nequist - Monte Sereno CA, US
Richard Brashears - San Jose CA, US
Assignee:

Cadence Design Systems, Inc. - San Jose CA
International Classification:

G06F 17/50
US Classification:

716 12, 716 13, 716 9, 716 10
Abstract:

Disclosed is an improved method, system, and article of manufacture for implementing routing for an electrical circuit and chip design. A routing architecture can be represented as a spectrum of different granular routing levels. Instead of routing based upon area, routing can be performed for specific routes or portions of routes. Different types of representation or levels of abstraction for the routing can be used for the same net or route. Partial topological reconfiguration, refinement, or rip-up can be performed for a portion of the integrated circuit design, where the portion is smaller than an entire route or net. Non-uniform levels of routing activities or resources may be applied to route the design. Prioritization may be used to route certain portions of the design with greater levels of detail, abstraction, or resources than other portions of the design.

Eric M Nequist